Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
166
Pulse-Width Modulator for Motor Control (PWMMC)
MOTOROLA
Pulse-Width Modulator for Motor Control
9.7.3 Output Port Control
When operating the PWMs using the OUTx bits (OUTCTL = 1), fault
protection applies as described in this section. Due to the absence of
periodic PWM cycles, fault conditions are cleared upon each CPU cycle
and the PWM outputs are re-enabled, provided all fault clearing
conditions are satisfied.
protection applies as described in this section. Due to the absence of
periodic PWM cycles, fault conditions are cleared upon each CPU cycle
and the PWM outputs are re-enabled, provided all fault clearing
conditions are satisfied.
Figure 9-30. PWM Software Disable
9.8 Initialization and the PWMEN Bit
For proper operation, all registers should be initialized and the LDOK bit
should be set before enabling the PWM via the PWMEN bit. When the
PWMEN bit is first set, a reload will occur immediately, setting the PWMF
flag and generating an interrupt if PWMINT is set. In addition, in
complementary mode, PWM value registers 1, 3, and 5 will be used for
the first PWM cycle if current sensing is selected.
should be set before enabling the PWM via the PWMEN bit. When the
PWMEN bit is first set, a reload will occur immediately, setting the PWMF
flag and generating an interrupt if PWMINT is set. In addition, in
complementary mode, PWM value registers 1, 3, and 5 will be used for
the first PWM cycle if current sensing is selected.
NOTE:
If the LDOK bit is not set when PWMEN is set after a RESET, the
prescaler and PWM values will be 0, but the modulus will be unknown.
If the LDOK bit is not set after the PWMEN bit has been cleared then set
(without a RESET), the modulus value that was last loaded will be used.
prescaler and PWM values will be 0, but the modulus will be unknown.
If the LDOK bit is not set after the PWMEN bit has been cleared then set
(without a RESET), the modulus value that was last loaded will be used.
If the dead-time register (DEADTM) is changed after PWMEN or
OUTCTL is set, an improper dead-time insertion could occur. However,
the dead-time can never be shorter than the specified value.
OUTCTL is set, an improper dead-time insertion could occur. However,
the dead-time can never be shorter than the specified value.
Because of the equals-comparator architecture of this PWM, the
modulus = 0 case is considered illegal. Therefore, the modulus register
modulus = 0 case is considered illegal. Therefore, the modulus register
PWM(S) ENABLED
PWM(S) ENABLED
PWM(S) DISABLED
DISABLE BIT