Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
236
Timer Interface B (TIMB)
MOTOROLA
Timer Interface B (TIMB)
12.5 Interrupts
These TIMB sources can generate interrupt requests:
•
TIMB overflow flag (TOF) — The timer counter value changes on
the falling edge of the internal bus clock. The timer overflow flag
(TOF) bit is set on the falling edge of the internal bus clock
following the timer rollover to $0000. The TIM overflow interrupt
enable bit, TOIE, enables TIM overflow interrupt requests. TOF
and TOIE are in the TIM status and control registers.
the falling edge of the internal bus clock. The timer overflow flag
(TOF) bit is set on the falling edge of the internal bus clock
following the timer rollover to $0000. The TIM overflow interrupt
enable bit, TOIE, enables TIM overflow interrupt requests. TOF
and TOIE are in the TIM status and control registers.
•
TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
12.6 Wait Mode
The WAIT instruction puts the MCU in low-power standby mode.
The TIMB remains active after the execution of a WAIT instruction. In
wait mode, the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
wait mode, the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
If TIMB functions are not required during wait mode, reduce power
consumption by stopping the TIMB before executing the WAIT
instruction.
consumption by stopping the TIMB before executing the WAIT
instruction.
12.7 I/O Signals
Port E shares three of its pins with the TIMB:
•
PTE4/ATD12 is an external clock input to the TIMB prescaler.
•
The two TIMB channel I/O pins are PTE1/TCH0B and
PTE2/TCH1B.
PTE2/TCH1B.