Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
284
Serial Communications Interface Module (SCI)
MOTOROLA
Serial Communications Interface Module (SCI)
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the PTF5/TxD pin. Setting
TE after the stop bit appears on PTF5/TxD causes data previously
written to the SCDR to be lost.
stop bit of the current character shifts out to the PTF5/TxD pin. Setting
TE after the stop bit appears on PTF5/TxD causes data previously
written to the SCDR to be lost.
A good time to toggle the TE bit is when the SCTE bit becomes set and
just before writing the next byte to the SCDR.
just before writing the next byte to the SCDR.
14.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
See
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
See
14.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI
transmitter:
transmitter:
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
14.4.3 Receiver
shows the structure of the SCI receiver.
14.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
M bit in SCI control register 1 (SCC1) determines character length.