Справочник Пользователя для Motorola MC68HC908MR16
Serial Communications Interface Module (SCI)
Functional Description
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
Advance Information
MOTOROLA
Serial Communications Interface Module (SCI)
289
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the PTF4/RxD pin can bring the receiver out of the standby
state:
conditions on the PTF4/RxD pin can bring the receiver out of the standby
state:
•
Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle
character on the PTF4/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.
character on the PTF4/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.
NOTE:
Clearing the WAKE bit after the PTF4/RxD pin has been idle can cause
the receiver to wake up immediately.
the receiver to wake up immediately.
14.4.3.6 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI
receiver:
receiver:
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
•
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PTF4/RxD pin. The idle
line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to
generate CPU interrupt requests.
consecutive logic 1s shifted in from the PTF4/RxD pin. The idle
line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to
generate CPU interrupt requests.