Справочник Пользователя для Motorola MC68HC908MR16
Computer Operating Properly (COP)
I/O Signals
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
Advance Information
MOTOROLA
Computer Operating Properly (COP)
325
The COP counter is a free-running, 6-bit counter preceded by the 13-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
18
–2
4
CGMXCLK cycles. With a 4.9152-MHz crystal, the COP timeout
period is 53.3 ms. Writing any value to location $FFFF before overflow
occurs clears the COP counter and prevents reset.
occurs clears the COP counter and prevents reset.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR). See
COP bit in the SIM reset status register (SRSR). See
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
16.4 I/O Signals
.
16.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
is equal to the crystal frequency.
16.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see
) clears the COP counter and clears bits 12–4 of the
SIM counter. Reading the COP control register returns the reset vector.
16.4.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096
CGMXCLK cycles after power-up.
CGMXCLK cycles after power-up.