Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
78
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
6.6.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
6.6.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
interrupt by:
•
Loading the instruction register with the software interrupt (SWI)
instruction
instruction
•
Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.