Справочник Пользователя для AMD Am188TMER
Interrupt Control Unit
8-29
8.4
SLAVE MODE OPERATION
When Slave mode is used, the microcontroller’s internal interrupt controller is used as a
slave controller to an external master interrupt controller. The internal interrupts are
monitored by the internal interrupt controller, while the external controller functions as the
system master interrupt controller.
slave controller to an external master interrupt controller. The internal interrupts are
monitored by the internal interrupt controller, while the external controller functions as the
system master interrupt controller.
On reset, the microcontroller is in Master mode. To activate Slave mode operation, bit 14
of the Relocation Register must be set (see Figure 4-2 on page 4-4).
of the Relocation Register must be set (see Figure 4-2 on page 4-4).
Because of pin limitations caused by the need to interface to an external 82C59A master,
the internal interrupt controller does not accept external inputs. However, there are enough
interrupt controller inputs (internally) to dedicate one to each timer. In Slave mode, each
timer interrupt source has its own mask bit, IS bit, and control word.
the internal interrupt controller does not accept external inputs. However, there are enough
interrupt controller inputs (internally) to dedicate one to each timer. In Slave mode, each
timer interrupt source has its own mask bit, IS bit, and control word.
The INT4, watchdog timer, and serial port interrupts are not available in Slave mode. In
Slave mode, each peripheral must be assigned a unique priority to ensure proper interrupt
controller operation. The programmer must assign correct priorities and initialize interrupt
control registers before enabling interrupts.
Slave mode, each peripheral must be assigned a unique priority to ensure proper interrupt
controller operation. The programmer must assign correct priorities and initialize interrupt
control registers before enabling interrupts.
8.4.1
Slave Mode Interrupt Nesting
Slave mode operation allows nesting of interrupt requests. When an interrupt is
acknowledged, the priority logic masks off all priority levels except those with equal or higher
priority.
acknowledged, the priority logic masks off all priority levels except those with equal or higher
priority.
8.4.2
Slave Mode Interrupt Controller Registers
The Interrupt Controller Registers for Slave mode are shown in Table 8-5. All registers can
be read and written, unless specified otherwise.
be read and written, unless specified otherwise.
Table 8-5
Interrupt Controller Registers in Slave Mode
Offset
Register
Mnemonic
Mnemonic
Register Name
Affected Pins
Comments
3Ah
T2INTCON
Timer 2 Interrupt Control
Interrupt Type XXXXX101
38h
T1INTCON
Timer 1 Interrupt Control
TMRIN1
TMROUT1
TMROUT1
Interrupt Type XXXXX100
36h
DMA1CON
DMA 1 Interrupt Control
Interrupt Type XXXXX011
34h
DMA0CON
DMA 0 Interrupt Control
Interrupt Type XXXXX010
32h
T0INTCON
Timer 0 Interrupt Control
TMRIN0
TMROUT0
TMROUT0
Interrupt Type XXXXX000
30h
INTSTS
Interrupt Status
2Eh
REQST
Interrupt Request
Read Only
2Ch
INSERV
In-Service
Read Only
2Ah
PRIMSK
Priority Mask
28h
IMASK
Interrupt Mask
22h
EOI
Specific EOI
Write Only
20h
INTVEC
Interrupt Vector