Справочник Пользователя для AMD Am188TMER
Features and Performance
1-6
1.3
APPLICATION CONSIDERATIONS
The integration enhancements of the Am186ER and Am188ER microcontrollers provide a
high-performance, low-system-cost solution for 16-bit embedded microcontroller designs.
high-performance, low-system-cost solution for 16-bit embedded microcontroller designs.
The internal 32-Kbyte RAM allows the manufacture of a complete embedded system using
only one external ROM device and a low-cost crystal, plus any voltage conversion or current
drivers required for I/O. Internal RAM is enabled and configured by using the Internal
Memory Chip Select (IMCS) Register described in Chapter 6, “Internal Memory.”
only one external ROM device and a low-cost crystal, plus any voltage conversion or current
drivers required for I/O. Internal RAM is enabled and configured by using the Internal
Memory Chip Select (IMCS) Register described in Chapter 6, “Internal Memory.”
The nonmultiplexed address bus (A19–A0) eliminates system-interface logic for external
memory, while the multiplexed address/data bus maintains the value of existing customer-
specific peripherals and circuits within the upgraded design.
memory, while the multiplexed address/data bus maintains the value of existing customer-
specific peripherals and circuits within the upgraded design.
The nonmultiplexed address bus is available in addition to the 80C186 and 80C188
microcontrollers’ multiplexed address/data bus (AD15–AD0). The two buses can operate
simultaneously, or the AD15–AD0 bus can be configured to operate only during the data
phase of a bus cycle. See the BHE/ADEN and RFSH2/ADEN pin descriptions in Chapter 3,
and see section 5.5.1 and section 5.5.2 for additional information regarding the AD15–AD0
address enabling and disabling.
microcontrollers’ multiplexed address/data bus (AD15–AD0). The two buses can operate
simultaneously, or the AD15–AD0 bus can be configured to operate only during the data
phase of a bus cycle. See the BHE/ADEN and RFSH2/ADEN pin descriptions in Chapter 3,
and see section 5.5.1 and section 5.5.2 for additional information regarding the AD15–AD0
address enabling and disabling.
Figure 1-3 illustrates a functional system design that uses the integrated peripheral set to
achieve high performance with reduced system cost.
achieve high performance with reduced system cost.
Figure 1-3
Basic Functional System Design
1.3.1
Clock Generation
The integrated PLL clock-generation circuitry of the Am186ER and Am188ER
microcontrollers allows operation at one times or four times the crystal frequency, in addition
to the one-half frequency operation required by 80C186 and 80C188 microcontrollers. The
design in Figure 1-3 achieves 40-MHz CPU operation with a 10-MHz crystal.
microcontrollers allows operation at one times or four times the crystal frequency, in addition
to the one-half frequency operation required by 80C186 and 80C188 microcontrollers. The
design in Figure 1-3 achieves 40-MHz CPU operation with a 10-MHz crystal.
The integrated PLL lowers system cost by reducing the cost of the crystal and reduces
electromagnetic interference (EMI) in the system.
electromagnetic interference (EMI) in the system.
X2
X1
RS-232
Level
Converter
TXD
RXD
UCS
WR
RD
WE
OE
CS
AD15–AD0
A19–A0
Serial Port
Am186ER
Microcontroller
10-MHz
Crystal
Address
Data
32 Kbyte
RAM
RAM
Timer 0–2
INT4–INT0
DMA 0–1
CLKOUTA
40 MHz
Am29F400
Flash