Справочник Пользователя для Xilinx 1.8
Endpoint Block Plus v1.8 for PCI Express
5
UG343 June 27, 2008
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Preface
About This Guide
The Endpoint Block Plus for PCI Express® Getting Started Guide provides information about
generating an Endpoint Block Plus for PCI Express (PCIe
generating an Endpoint Block Plus for PCI Express (PCIe
®
) core, customizing and
simulating the core using the provided example design, and running the design files
through implementation using the Xilinx tools.
through implementation using the Xilinx tools.
Contents
This guide contains the following chapters:
•
Preface, “About this Guide,”
introduces the organization and purpose of this guide
and the conventions used in this document.
•
describes the core and related information, including
system requirements, recommended design experience, additional resources,
technical support, and submitting feedback to Xilinx.
technical support, and submitting feedback to Xilinx.
•
provides instructions for selecting a license option for
the core.
•
generating, simulating, and implementing the example design and the dual core
example design using the demonstration test bench.
example design using the demonstration test bench.
•
defines additional considerations
when implementing the example design.
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention
Meaning or Use
Example
Courier font
Messages, prompts, and
program files that the system
displays
program files that the system
displays
speed grade: - 100
Courier bold
Literal commands you enter in
a syntactical statement
a syntactical statement
ngdbuild
design_name