Инструкции для Atmel Xplained Evaluation Board AT32UC3A3-XPLD

Atmel

Модели

AT32UC3A3-XPLD

Техническая Спецификация (English)Техническая Спецификация (English)Техническая Спецификация (English)

Техническая Спецификация (AT32UC3A3-XPLD)

Содержание

Техническая Спецификация (AT32UC3A3-XPLD)

Размер:

723,3 КБ
Страницы:

15
Язык:

English

Просмотреть

Техническая Спецификация (AT32UC3A3-XPLD)

Техническая Спецификация (AT32UC3A3-XPLD)

Размер:

314,7 КБ
Страницы:

10
Язык:

English

Просмотреть

Техническая Спецификация (AT32UC3A3-XPLD)

Содержание

1. Description
3
2. Overview
4
- 2.1 Block Diagram
  4
- 2.2 Configuration Summary
  5
3. Package and Pinout
6
- 3.1 Package
  6
- 3.2 Peripheral Multiplexing on I/O lines
  9
- 3.3 Signal Descriptions
  14
- 3.4 I/O Line Considerations
  19
  - 3.4.1 JTAG Pins
    19
  - 3.4.2 RESET_N Pin
    19
  - 3.4.3 TWI Pins
    19
  - 3.4.4 GPIO Pins
    19
- 3.5 Power Considerations
  20
  - 3.5.1 Power Supplies
    20
  - 3.5.2 Voltage Regulator
    20
4. Processor and Architecture
21
- 4.1 Features
  21
- 4.2 AVR32 Architecture
  21
- 4.3 The AVR32UC CPU
  22
- 4.4 Programming Model
  26
- 4.5 Exceptions and Interrupts
  30
- 4.6 Module Configuration
  34
5. Memories
35
- 5.1 Embedded Memories
  35
- 5.2 Physical Memory Map
  35
- 5.3 Peripheral Address Map
  36
- 5.4 CPU Local Bus Mapping
  38
6. Boot Sequence
40
- 6.1 Starting of Clocks
  40
- 6.2 Fetching of Initial Instructions
  40
7. Power Manager (PM)
41
- 7.1 Features
  41
- 7.2 Overview
  41
- 7.3 Block Diagram
  42
- 7.4 Product Dependencies
  43
  - 7.4.1 I/O Lines
    43
  - 7.4.2 Interrupt
    43
- 7.5 Functional Description
  43
- 7.6 User Interface
  55
8. Real Time Counter (RTC)
80
- 8.1 Features
  80
- 8.2 Overview
  80
- 8.3 Block Diagram
  80
- 8.4 Product Dependencies
  80
  - 8.4.1 Power Management
    81
  - 8.4.2 Clocks
    81
  - 8.4.3 Interrupts
    81
  - 8.4.4 Debug Operation
    81
- 8.5 Functional Description
  81
  - 8.5.1 RTC Operation
    81
    - 8.5.1.1 Source clock
      81
    - 8.5.1.2 Counter operation
      81
    - 8.5.1.3 RTC interrupt
      82
    - 8.5.1.4 RTC wakeup
      82
    - 8.5.1.5 Busy bit
      82
- 8.6 User Interface
  83
9. Watchdog Timer (WDT)
92
- 9.1 Features
  92
- 9.2 Overview
  92
- 9.3 Block Diagram
  92
- 9.4 Product Dependencies
  92
  - 9.4.1 Power Management
    92
  - 9.4.2 Clocks
    92
  - 9.4.3 Debug Operation
    92
- 9.5 Functional Description
  93
- 9.6 User Interface
  93
  - 9.6.1 Control Register
    94
  - 9.6.2 Clear Register
    95
10. Interrupt Controller (INTC)
96
- 10.1 Features
  96
- 10.2 Overview
  96
- 10.3 Block Diagram
  96
- 10.4 Product Dependencies
  97
  - 10.4.1 Power Management
    97
  - 10.4.2 Clocks
    97
  - 10.4.3 Debug Operation
    97
- 10.5 Functional Description
  97
- 10.6 User Interface
  100
- 10.7 Interrupt Request Signal Map
  104
11. External Interrupt Controller (EIC)
107
- 11.1 Features
  107
- 11.2 Overview
  107
- 11.3 Block Diagram
  108
- 11.4 I/O Lines Description
  108
- 11.5 Product Dependencies
  108
  - 11.5.1 I/O Lines
    108
  - 11.5.2 Power Management
    108
  - 11.5.3 Clocks
    109
  - 11.5.4 Interrupts
    109
  - 11.5.5 Debug Operation
    109
- 11.6 Functional Description
  109
- 11.7 User Interface
  113
  - 11.7.1 Interrupt Enable Register
    114
  - 11.7.2 Interrupt Disable Register
    115
  - 11.7.3 Interrupt Mask Register
    116
  - 11.7.4 Interrupt Status Register
    117
  - 11.7.5 Interrupt Clear Register
    118
  - 11.7.6 Mode Register
    119
  - 11.7.7 Edge Register
    120
  - 11.7.8 Level Register
    121
  - 11.7.9 Filter Register
    122
  - 11.7.10 Test Register
    123
  - 11.7.11 Asynchronous Register
    124
  - 11.7.12 Scan Register
    125
  - 11.7.13 Enable Register
    126
  - 11.7.14 Disable Register
    127
  - 11.7.15 Control Register
    128
- 11.8 Module Configuration
  129
12. Flash Controller (FLASHC)
130
- 12.1 Features
  130
- 12.2 Overview
  130
- 12.3 Product dependencies
  130
  - 12.3.1 Power Manager
    130
  - 12.3.2 Interrupt Controller
    130
- 12.4 Functional description
  131
- 12.5 Flash commands
  134
- 12.6 General-purpose fuse bits
  136
- 12.7 Security bit
  138
- 12.8 User interface
  139
- 12.9 Fuses Settings
  147
  - 12.9.1 Flash General Purpose Fuse Register Low (FGPFRLO)
    147
  - 12.9.2 Default Fuse Value
    147
- 12.10 Serial number in the factory page
  148
- 12.11 Module configuration
  148
13. HSB Bus Matrix (HMATRIX)
149
- 13.1 Features
  149
- 13.2 Overview
  149
- 13.3 Product Dependencies
  149
  - 13.3.1 Clocks
    149
- 13.4 Functional Description
  149
- 13.5 User Interface
  153
- 13.6 Bus Matrix Connections
  161
14. External Bus Interface (EBI)
163
- 14.1 Features
  163
- 14.2 Overview
  163
- 14.3 Block Diagram
  164
- 14.4 I/O Lines Description
  165
- 14.5 Product Dependencies
  166
  - 14.5.1 I/O Lines
    166
  - 14.5.2 Power Management
    166
  - 14.5.3 Clocks
    166
  - 14.5.4 Interrupts
    167
  - 14.5.5 HMATRIX
    167
- 14.6 Functional Description
  168
- 14.7 Application Example
  175
  - 14.7.1 Hardware Interface
    175
  - 14.7.2 Connection Examples
    177
15. Static Memory Controller (SMC)
178
- 15.1 Features
  178
- 15.2 Overview
  178
- 15.3 Block Diagram
  179
- 15.4 I/O Lines Description
  179
- 15.5 Product Dependencies
  179
  - 15.5.1 I/O Lines
    180
  - 15.5.2 Clocks
    180
- 15.6 Functional Description
  180
- 15.7 User Interface
  212
  - 15.7.1 Setup Register
    213
  - 15.7.2 Pulse Register
    214
  - 15.7.3 Cycle Register
    215
  - 15.7.4 Mode Register
    216
16. SDRAM Controller (SDRAMC)
219
- 16.1 Features
  219
- 16.2 Overview
  219
- 16.3 Block Diagram
  220
- 16.4 I/O Lines Description
  220
- 16.5 Application Example
  221
  - 16.5.1 Hardware Interface
    221
  - 16.5.2 Software Interface
    221
    - 16.5.2.1 16-bit memory data bus width
      222
- 16.6 Product Dependencies
  222
  - 16.6.1 I/O Lines
    222
  - 16.6.2 Power Management
    222
  - 16.6.3 Clocks
    223
  - 16.6.4 Interrupts
    223
- 16.7 Functional Description
  223
- 16.8 User Interface
  232
17. Error Corrected Code Controller (ECCHRS)
246
- 17.1 Features
  246
- 17.2 Overview
  246
- 17.3 Block Diagram
  247
- 17.4 Product Dependencies
  247
  - 17.4.1 I/O Lines
    247
  - 17.4.2 Power Management
    247
  - 17.4.3 Clocks
    247
  - 17.4.4 Interrupts
    247
- 17.5 Functional Description
  248
  - 17.5.1 Write Access
    248
  - 17.5.2 Read Access
    248
- 17.6 User Interface
  254
- 17.7 Module Configuration
  280
18. Peripheral DMA Controller (PDCA)
281
- 18.1 Features
  281
- 18.2 Overview
  281
- 18.3 Block Diagram
  282
- 18.4 Product Dependencies
  282
  - 18.4.1 Power Management
    282
  - 18.4.2 Clocks
    282
  - 18.4.3 Interrupts
    282
- 18.5 Functional Description
  283
  - 18.5.1 Basic Operation
    283
  - 18.5.2 Memory Pointer
    283
  - 18.5.3 Transfer Counter
    283
  - 18.5.4 Reload Registers
    283
  - 18.5.5 Peripheral Selection
    284
  - 18.5.6 Transfer Size
    284
  - 18.5.7 Enabling and Disabling
    284
  - 18.5.8 Interrupts
    284
  - 18.5.9 Priority
    284
  - 18.5.10 Error Handling
    284
- 18.6 Performance Monitors
  285
  - 18.6.1 Measuring mechanisms
    285
- 18.7 User Interface
  286
- 18.8 Module Configuration
  314
  - 18.8.1 DMA Handshake Signals
    314
19. DMA Controller (DMACA)
316
- 19.1 Features
  316
- 19.2 Overview
  316
- 19.3 Block Diagram
  317
- 19.4 Product Dependencies
  317
  - 19.4.1 I/O Lines
    317
  - 19.4.2 Power Management
    317
  - 19.4.3 Clocks
    317
  - 19.4.4 Interrupts
    317
  - 19.4.5 Peripherals
    317
- 19.5 Functional Description
  318
  - 19.5.1 Basic Definitions
    318
- 19.6 Arbitration for HSB Master Interface
  323
- 19.7 Memory Peripherals
  323
- 19.8 Handshaking Interface
  323
  - 19.8.1 Software Handshaking
    324
    - 19.8.1.1 Burst Transactions
      324
    - 19.8.1.2 Single Transactions
      324
  - 19.8.2 Hardware Handshaking
    324
    - 19.8.2.1 External DMA Request Definition
      325
- 19.9 DMACA Transfer Types
  325
  - 19.9.1 Multi-block Transfers
    326
  - 19.9.2 Ending Multi-block Transfers
    328
- 19.10 Programming a Channel
  329
  - 19.10.1 Programming Examples
    329
- 19.11 Disabling a Channel Prior to Transfer Completion
  346
  - 19.11.1 Abnormal Transfer Termination
    347
- 19.12 User Interface
  348
- 19.13 Module Configuration
  380
20. General-Purpose Input/Output Controller (GPIO)
381
- 20.1 Features
  381
- 20.2 Overview
  381
- 20.3 Block Diagram
  381
- 20.4 Product Dependencies
  381
  - 20.4.1 Module Configuration
    382
  - 20.4.2 Clocks
    382
  - 20.4.3 Interrupts
    382
- 20.5 Functional Description
  382
  - 20.5.1 Basic Operation
    383
  - 20.5.2 Advanced Operation
    384
    - 20.5.2.1 Pull-up resistor control
      384
    - 20.5.2.2 Input glitch filter
      384
  - 20.5.3 Interrupts
    385
  - 20.5.4 Interrupt Timings
    385
- 20.6 User Interface
  386
- 20.7 Programming Examples
  401
  - 20.7.1 8-bit LED-Chaser
    401
  - 20.7.2 Configuration of USART pins
    401
- 20.8 Module configuration
  403
21. Serial Peripheral Interface (SPI)
404
- 21.1 Features
  404
- 21.2 Overview
  404
- 21.3 Block Diagram
  405
- 21.4 Application Block Diagram
  405
- 21.5 I/O Lines Description
  406
- 21.6 Product Dependencies
  406
  - 21.6.1 I/O Lines
    406
  - 21.6.2 Clocks
    406
  - 21.6.3 Interrupts
    406
- 21.7 Functional Description
  406
- 21.8 User Interface
  417
- 21.9 Module Configuration
  443
22. Two-wire Slave Interface (TWIS)
444
- 22.1 Features
  444
- 22.2 Overview
  444
- 22.3 List of Abbreviations
  445
- 22.4 Block Diagram
  445
- 22.5 Application Block Diagram
  446
- 22.6 I/O Lines Description
  446
- 22.7 Product Dependencies
  446
  - 22.7.1 I/O Lines
    446
  - 22.7.2 Power Management
    447
  - 22.7.3 Clocks
    447
  - 22.7.4 DMA
    447
  - 22.7.5 Interrupts
    447
  - 22.7.6 Debug Operation
    447
- 22.8 Functional Description
  447
- 22.9 User Interface
  457
- 22.10 Module Configuration
  473
23. Two-wire Master Interface (TWIM)
474
- 23.1 Features
  474
- 23.2 Overview
  474
- 23.3 List of Abbreviations
  475
- 23.4 Block Diagram
  475
- 23.5 Application Block Diagram
  476
- 23.6 I/O Lines Description
  476
- 23.7 Product Dependencies
  476
  - 23.7.1 I/O Lines
    476
  - 23.7.2 Power Management
    476
  - 23.7.3 Clocks
    477
  - 23.7.4 DMA
    477
  - 23.7.5 Interrupts
    477
  - 23.7.6 Debug Operation
    477
- 23.8 Functional Description
  478
- 23.9 User Interface
  490
- 23.10 Module Configuration
  507
24. Synchronous Serial Controller (SSC)
508
- 24.1 Features
  508
- 24.2 Overview
  508
- 24.3 Block Diagram
  509
- 24.4 Application Block Diagram
  509
- 24.5 I/O Lines Description
  510
- 24.6 Product Dependencies
  510
  - 24.6.1 I/O Lines
    510
  - 24.6.2 Clocks
    510
  - 24.6.3 Interrupts
    510
- 24.7 Functional Description
  510
  - 24.7.1 Clock Management
    511
  - 24.7.2 Transmitter Operations
    514
  - 24.7.3 Receiver Operations
    515
  - 24.7.4 Start
    516
  - 24.7.5 Frame Sync
    518
    - 24.7.5.1 Frame sync data
      518
    - 24.7.5.2 Frame sync edge detection
      518
  - 24.7.6 Receive Compare Modes
    519
    - 24.7.6.1 Compare functions
      519
  - 24.7.7 Data Framing Format
    519
  - 24.7.8 Loop Mode
    521
  - 24.7.9 Interrupt
    521
- 24.8 SSC Application Examples
  522
- 24.9 User Interface
  524
25. Universal Synchronous Asynchronous Receiver Transmitter (USART)
546
- 25.1 Features
  546
- 25.2 Overview
  546
- 25.3 Block Diagram
  547
- 25.4 I/O Lines Description
  548
- 25.5 Product Dependencies
  548
  - 25.5.1 I/O Lines
    548
  - 25.5.2 Clocks
    549
  - 25.5.3 Interrupts
    549
- 25.6 Functional Description
  550
- 25.7 User Interface
  593
26.
621
- 26.1 Module Configuration
  622
  - 26.1.1 Clock Connections
    622
  - 26.1.2 Register Reset Values
    623
27. Hi-Speed USB Interface (USBB)
624
- 27.1 Features
  624
- 27.2 Overview
  624
- 27.3 Block Diagram
  625
- 27.4 Application Block Diagram
  626
  - 27.4.1 Device Mode
    626
    - 27.4.1.1 Bus-Powered device
      626
    - 27.4.1.2 Self-Powered device
      627
  - 27.4.2 Host Mode
    627
- 27.5 I/O Lines Description
  628
- 27.6 Product Dependencies
  629
  - 27.6.1 I/O Lines
    629
  - 27.6.2 Clocks
    629
  - 27.6.3 Interrupts
    629
- 27.7 Functional Description
  630
  - 27.7.1 USB General Operation
    630
    - 27.7.1.1 Introduction
      630
    - 27.7.1.2 Power-On and reset
      630
    - 27.7.1.3 Interrupts
      631
    - 27.7.1.4 MCU Power modes
      633
      - • Run mode
        633
      - • Idle mode
        633
      - • Frozen mode
        633
      - • Standby, Stop, DeepStop and Static modes
        633
      - • USB clock frozen
        633
      - • USB Suspend mode
        634
    - 27.7.1.5 Speed control
      634
      - • Device mode
        634
      - • Host mode
        634
    - 27.7.1.6 DPRAM management
      634
    - 27.7.1.7 Pad Suspend
      636
    - 27.7.1.8 Plug-In detection
      637
    - 27.7.1.9 ID detection
      637
  - 27.7.2 USB Device Operation
    639
    - 27.7.2.1 Introduction
      639
    - 27.7.2.2 Power-On and reset
      639
    - 27.7.2.3 USB reset
      639
    - 27.7.2.4 Endpoint reset
      640
    - 27.7.2.5 Endpoint activation
      640
    - 27.7.2.6 Address setup
      641
    - 27.7.2.7 Suspend and wake-up
      642
    - 27.7.2.8 Detach
      642
    - 27.7.2.9 Remote wake-up
      642
    - 27.7.2.10 STALL request
      642
      - • Special considerations for control endpoints
        643
      - • STALL handshake and retry mechanism
        643
    - 27.7.2.11 Management of control endpoints
      643
      - • Overview
        643
      - • Control write
        643
      - • Control read
        644
    - 27.7.2.12 Management of IN endpoints
      645
      - • Overview
        645
      - • Detailed description
        646
    - 27.7.2.13 Management of OUT endpoints
      647
      - • Overview
        647
      - • Detailed description
        648
    - 27.7.2.14 Underflow
      649
    - 27.7.2.15 Overflow
      649
    - 27.7.2.16 HB IsoIn error
      649
    - 27.7.2.17 HB IsoFlush
      649
    - 27.7.2.18 CRC error
      650
    - 27.7.2.19 Interrupts
      650
      - • Global interrupts
        650
      - • Endpoint interrupts
        650
      - • DMA interrupts
        651
    - 27.7.2.20 Test Modes
      651
  - 27.7.3 USB Host Operation
    652
    - 27.7.3.1 Description of pipes
      652
    - 27.7.3.2 Power-On and reset
      652
    - 27.7.3.3 Device detection
      653
    - 27.7.3.4 USB reset
      653
    - 27.7.3.5 Pipe reset
      653
    - 27.7.3.6 Pipe activation
      654
    - 27.7.3.7 Address setup
      654
    - 27.7.3.8 Remote wake-up
      655
    - 27.7.3.9 Management of control pipes
      655
    - 27.7.3.10 Management of IN pipes
      655
    - 27.7.3.11 Management of OUT pipes
      656
    - 27.7.3.12 CRC error
      658
    - 27.7.3.13 Interrupts
      658
      - • Global interrupts
        658
      - • Pipe interrupts
        659
      - • DMA interrupts
        659
  - 27.7.4 USB DMA Operation
    660
- 27.8 User Interface
  665
- 27.9 Module Configuration
  748
28. Timer/Counter (TC)
749
- 28.1 Features
  749
- 28.2 Overview
  749
- 28.3 Block Diagram
  750
- 28.4 I/O Lines Description
  750
- 28.5 Product Dependencies
  750
  - 28.5.1 I/O Lines
    750
  - 28.5.2 Power Management
    751
  - 28.5.3 Clocks
    751
  - 28.5.4 Interrupts
    751
  - 28.5.5 Debug Operation
    751
- 28.6 Functional Description
  751
  - 28.6.1 TC Description
    751
    - 28.6.1.1 Channel I/O Signals
      751
    - 28.6.1.2 16-bit counter
      751
    - 28.6.1.3 Clock selection
      752
    - 28.6.1.4 Clock control
      752
    - 28.6.1.5 TC operating modes
      753
    - 28.6.1.6 Trigger
      754
  - 28.6.2 Capture Operating Mode
    754
    - 28.6.2.1 Capture registers A and B
      754
    - 28.6.2.2 Trigger conditions
      755
  - 28.6.3 Waveform Operating Mode
    757
    - 28.6.3.1 Waveform selection
      757
    - 28.6.3.2 WAVSEL = 0
      759
    - 28.6.3.3 WAVSEL = 2
      760
    - 28.6.3.4 WAVSEL = 1
      761
    - 28.6.3.5 WAVSEL = 3
      763
    - 28.6.3.6 External event/trigger conditions
      764
    - 28.6.3.7 Output controller
      764
- 28.7 User Interface
  766
- 28.8 Module Configuration
  789
  - 28.8.1 Clock Connections
    789
29. Analog-to-Digital Converter (ADC)
790
- 29.1 Features
  790
- 29.2 Overview
  790
- 29.3 Block Diagram
  791
- 29.4 I/O Lines Description
  791
- 29.5 Product Dependencies
  791
  - 29.5.1 I/O Lines
    791
  - 29.5.2 Power Management
    792
  - 29.5.3 Clocks
    792
  - 29.5.4 Interrupts
    792
  - 29.5.5 Analog Inputs
    792
  - 29.5.6 Timer Triggers
    792
- 29.6 Functional Description
  792
- 29.7 User Interface
  797
- 29.8 Module Configuration
  810
30. HSB Bus Performance Monitor (BUSMON)
811
- 30.1 Features
  811
- 30.2 Overview
  811
- 30.3 Block Diagram
  811
- 30.4 Product Dependencies
  812
  - 30.4.1 Clocks
    812
- 30.5 Functional Description
  812
- 30.6 User interface
  813
- 30.7 Module Configuration
  820
31. MultiMedia Card Interface (MCI)
821
- 31.1 Features
  821
- 31.2 Overview
  821
- 31.3 Block Diagram
  822
- 31.4 I/O Lines Description
  823
- 31.5 Product Dependencies
  823
  - 31.5.1 Power Management
    823
  - 31.5.2 I/O Lines
    823
  - 31.5.3 Clocks
    823
  - 31.5.4 Interrupt
    823
- 31.6 Functional Description
  823
- 31.7 User Interface
  841
- 31.8 Module Configuration
  869
32. Memory Stick Interface (MSI)
870
- 32.1 Features
  870
- 32.2 Overview
  870
- 32.3 Block Diagram
  871
- 32.4 Product Dependencies
  871
  - 32.4.1 GPIO
    871
  - 32.4.2 Power Manager
    871
  - 32.4.3 Interrupt Controller
    872
  - 32.4.4 DMA Controller (DMACA)
    872
- 32.5 Connection to a Memory Stick
  872
- 32.6 Functional Description
  873
- 32.7 User Interface
  876
  - 32.7.1 Command register
    877
  - 32.7.2 Data register
    879
  - 32.7.3 Status register
    880
  - 32.7.4 System register
    882
  - 32.7.5 Interrupt Status register
    884
  - 32.7.6 Interrupt Status Clear register
    885
  - 32.7.7 Interrupt Enable register
    886
  - 32.7.8 Interrupt Disable register
    887
  - 32.7.9 Interrupt Mask register
    888
  - 32.7.10 Version Register
    889
33. Advanced Encryption Standard (AES)
890
- 33.1 Features
  890
- 33.2 Overview
  890
- 33.3 Product Dependencies
  890
  - 33.3.1 Power Management
    890
  - 33.3.2 Clocks
    891
  - 33.3.3 Interrupts
    891
- 33.4 Functional Description
  891
  - 33.4.1 Operation Modes
    891
  - 33.4.2 Start Modes
    892
    - 33.4.2.1 Manual mode
      892
    - 33.4.2.2 Automatic mode
      892
    - 33.4.2.3 DMA mode
      893
  - 33.4.3 Last Output Data Mode
    893
    - 33.4.3.1 Manual and automatic modes
      894
    - 33.4.3.2 DMA mode
      894
  - 33.4.4 Security Features
    896
    - 33.4.4.1 Countermeasures
      896
    - 33.4.4.2 Unspecified register access detection
      896
- 33.5 User Interface
  897
- 33.6 Module Configuration
  912
34. Audio Bitstream DAC (ABDAC)
913
- 34.1 Features
  913
- 34.2 Overview
  913
- 34.3 Block Diagram
  914
- 34.4 I/O Lines Description
  914
- 34.5 Product Dependencies
  914
  - 34.5.1 I/O Lines
    914
  - 34.5.2 Clocks
    915
  - 34.5.3 Interrupts
    915
- 34.6 Functional Description
  915
  - 34.6.1 How to Initialize the Module
    915
  - 34.6.2 Data Format
    915
  - 34.6.3 Data Swapping
    916
  - 34.6.4 Peripheral DMA Controller
    916
  - 34.6.5 Construction
    916
  - 34.6.6 Equalization Filter
    916
  - 34.6.7 Interpolation Filter
    916
  - 34.6.8 Sigma-Delta Modulator
    916
  - 34.6.9 Frequency Response
    917
- 34.7 User Interface
  918
35. Programming and Debugging
926
- 35.1 Overview
  926
- 35.2 Service Access Bus
  926
  - 35.2.1 SAB address map
    926
  - 35.2.2 SAB security restrictions
    926
    - 35.2.2.1 Security measure and control location
      927
- 35.3 On-Chip Debug (OCD)
  928
  - 35.3.1 Features
    928
  - 35.3.2 Overview
    928
  - 35.3.3 Block Diagram
    929
  - 35.3.4 JTAG-based Debug Features
    929
    - 35.3.4.1 Debug Communication Channel
      930
    - 35.3.4.2 breakpoints
      930
    - 35.3.4.3 OCD mode
      931
    - 35.3.4.4 monitor mode
      931
    - 35.3.4.5 program counter monitoring
      931
  - 35.3.5 Memory Service Unit
    931
    - 35.3.5.1 Cyclic Redundancy Check (CRC)
      931
    - 35.3.5.2 NanoTrace
      931
  - 35.3.6 AUX-based Debug Features
    931
- 35.4 JTAG and Boundary-scan (JTAG)
  935
  - 35.4.1 Features
    935
  - 35.4.2 Overview
    935
  - 35.4.3 Block Diagram
    936
  - 35.4.4 I/O Lines Description
    936
  - 35.4.5 Product Dependencies
    936
    - 35.4.5.1 Power Management
      937
    - 35.4.5.2 Clocks
      937
  - 35.4.6 JTAG Interface
    937
  - 35.4.7 How to Initialize the Module
    939
  - 35.4.8 Typical Sequence
    939
    - 35.4.8.1 Scanning in JTAG Instruction
      939
    - 35.4.8.2 Scanning in/out Data
      939
  - 35.4.9 Boundary-scan
    940
  - 35.4.10 Service Access Bus
    940
    - 35.4.10.1 SAB Address Mode
      941
    - 35.4.10.2 Block Transfer
      941
    - 35.4.10.3 Canceling a SAB Access
      941
    - 35.4.10.4 Busy Reporting
      941
    - 35.4.10.5 Error Reporting
      942
    - 35.4.10.6 Protected Reporting
      942
- 35.5 JTAG Instruction Summary
  943
  - 35.5.1 Security Restrictions
    943
    - 35.5.1.1 Notation
      944
  - 35.5.2 Public JTAG Instructions
    945
    - 35.5.2.1 IDCODE
      945
    - 35.5.2.2 SAMPLE_PRELOAD
      945
    - 35.5.2.3 EXTEST
      946
    - 35.5.2.4 INTEST
      947
    - 35.5.2.5 CLAMP
      947
    - 35.5.2.6 BYPASS
      948
  - 35.5.3 Private JTAG Instructions
    948
    - 35.5.3.1 NEXUS_ACCESS
      948
    - 35.5.3.2 MEMORY_SERVICE
      949
    - 35.5.3.3 MEMORY_SIZED_ACCESS
      950
    - 35.5.3.4 MEMORY_WORD_ACCESS
      952
    - 35.5.3.5 MEMORY_BLOCK_ACCESS
      953
    - 35.5.3.6 CANCEL_ACCESS
      954
    - 35.5.3.7 SYNC
      954
    - 35.5.3.8 AVR_RESET
      955
    - 35.5.3.9 CHIP_ERASE
      956
    - 35.5.3.10 HALT
      956
  - 35.5.4 JTAG Data Registers
    958
36. Electrical Characteristics
960
- 36.1 Absolute Maximum Ratings*
  960
- 36.2 DC Characteristics
  961
  - 36.2.1 I/O Pin Output Level Typical Characteristics
    962
- 36.3 I/O pin Characteristics
  962
- 36.4 Regulator characteristics
  963
- 36.5 Analog characteristics
  964
  - 36.5.1 ADC
    964
  - 36.5.2 BOD
    964
  - 36.5.3 Reset Sequence
    965
  - 36.5.4 RESET_N Characteristics
    967
- 36.6 Power Consumption
  968
  - 36.6.1 Power Consumtion for Different Sleep Modes
    969
- 36.7 System Clock Characteristics
  971
- 36.8 Oscillator Characteristics
  972
- 36.9 ADC Characteristics
  974
- 36.10 USB Transceiver Characteristics
  975
- 36.11 EBI Timings
  977
  - 36.11.1 SMC Signals
    977
  - 36.11.2 SDRAM Signals
    980
- 36.12 JTAG Characteristics
  983
  - 36.12.1 JTAG Interface Signals
    983
- 36.13 SPI Characteristics
  984
- 36.14 MCI
  986
- 36.15 Flash Memory Characteristics
  987
37. Mechanical Characteristics
988
- 37.1 Thermal Considerations
  988
  - 37.1.1 Thermal Data
    988
  - 37.1.2 Junction Temperature
    988
- 37.2 Package Drawings
  989
- 37.3 Soldering Profile
  992
38. Ordering Information
993
39. Errata
994
- 39.1 Rev. H
  994
  - 39.1.1 General
    994
  - 39.1.2 Processor and Architecture
    994
  - 39.1.3 USB
    994
  - 39.1.4 ADC
    995
  - 39.1.5 USART
    995
  - 39.1.6 HMATRIX
    997
  - 39.1.7 TWIM
    997
  - 39.1.8 FLASHC
    998
- 39.2 Rev. E
  998
  - 39.2.1 General
    998
  - 39.2.2 USB
    999
  - 39.2.3 ADC
    1000
  - 39.2.4 USART
    1000
  - 39.2.5 HMATRIX
    1002
  - 39.2.6 TWIM
    1002
  - 39.2.7 FLASHC
    1003
- 39.3 Rev. D
  1004
  - 39.3.1 General
    1004
  - 39.3.2 USB
    1005
  - 39.3.3 ADC
    1005
  - 39.3.4 USART
    1005
  - 39.3.5 HMATRIX
    1008
  - 39.3.6 TWIM
    1008
  - 39.3.7 MCI
    1008
  - 39.3.8 SSC
    1009
  - 39.3.9 FLASHC
    1009
40. Datasheet Revision History
1010
- 40.1 Rev. H– 10/12
  1010
- 40.2 Rev. G– 11/11
  1010
- 40.3 Rev. F – 08/11
  1010
- 40.4 Rev. E – 06/11
  1010
- 40.5 Rev. D – 04/11
  1010
- 40.6 Rev. C – 03/10
  1010
- 40.7 Rev. B – 08/09
  1011
- 40.8 Rev. A – 03/09
  1011

Техническая Спецификация (AT32UC3A3-XPLD)

Размер:

14,8 МБ
Страницы:

1021
Язык:

English

Просмотреть