Инструкции для Compaq ECQD2KCTE

Содержание

• Table of Contents

  3
  • 1 Introduction

    3
  • 2 Basic Architecture

    3
  • 3 Instruction Formats

    4
  • 4 Instruction Descriptions

    4
  • 5 System Architecture and Programming Implications

    7
  • 6 Common PALcode Architecture

    7
  • 7 Console Subsystem Overview

    8
  • 8 Input/Output Overview

    8
  • 9 OpenVMS Alpha

    8
  • 10 Digital UNIX

    8
  • 11 Windows NT Alpha

    8
  • A Software Considerations

    8
  • B IEEE Floating-Point Conformance

    9
  • C Instruction Summary

    9
  • D Registered System and Processor Identifiers

    9
  • E Waivers and Implementation-Dependent Functionality

    9
• Figures

  11
• Tables

  12
• Preface

  15
• Introduction

  17
  • 1.1 The Alpha Approach to RISC Architecture

    17
  • 1.2 Data Format Overview

    19
  • 1.3 Instruction Format Overview

    20
  • 1.4 Instruction Overview

    20
  • 1.5 Instruction Set Characteristics

    22
  • 1.6 Terminology and Conventions

    22
    • 1.6.1 Numbering

      23
    • 1.6.2 Security Holes

      23
    • 1.6.3 UNPREDICTABLE and UNDEFINED

      23
    • 1.6.4 Ranges and Extents

      24
    • 1.6.5 ALIGNED and UNALIGNED

      24
    • 1.6.6 Must Be Zero (MBZ)

      25
    • 1.6.7 Read As Zero (RAZ)

      25
    • 1.6.8 Should Be Zero (SBZ)

      25
    • 1.6.9 Ignore (IGN)

      25
    • 1.6.10 Implementation Dependent (IMP)

      25
    • 1.6.11 Illustration Conventions

      25
    • 1.6.12 Macro Code Example Conventions

      25
• Basic Architecture

  27
  • 2.1 Addressing

    27
  • 2.2 Data Types

    27
    • 2.2.1 Byte

      27
    • 2.2.2 Word

      27
    • 2.2.3 Longword

      28
    • 2.2.4 Quadword

      28
    • 2.2.5 VAX Floating-Point Formats

      29
      • 2.2.5.1 F_floating

        29
      • 2.2.5.2 G_floating

        30
      • 2.2.5.3 D_floating

        31
    • 2.2.6 IEEE Floating-Point Formats

      32
      • 2.2.6.1 S_Floating

        33
      • 2.2.6.2 T_floating

        34
      • 2.2.6.3 X_Floating

        35
    • 2.2.7 Longword Integer Format in Floating-Point Unit

      37
    • 2.2.8 Quadword Integer Format in Floating-Point Unit

      38
    • 2.2.9 Data Types with No Hardware Support

      38
  • 2.3 Big-Endian Addressing Support

    39
• Instruction Formats

  41
  • 3.1 Alpha Registers

    41
    • 3.1.1 Program Counter

      41
    • 3.1.2 Integer Registers

      41
    • 3.1.3 Floating-Point Registers

      42
    • 3.1.4 Lock Registers

      42
    • 3.1.5 Processor Cycle Counter (PCC) Register

      43
    • 3.1.6 Optional Registers

      43
      • 3.1.6.1 Memory Prefetch Registers

        43
      • 3.1.6.2 VAX Compatibility Register

        43
  • 3.2 Notation

    43
    • 3.2.1 Operand Notation

      44
    • 3.2.2 Instruction Operand Notation

      45
      • 3.2.2.1 Operand Name Notation

        45
      • 3.2.2.2 Operand Access Type Notation

        45
      • 3.2.2.3 Operand Data Type Notation

        46
    • 3.2.3 Operators

      46
    • 3.2.4 Notation Conventions

      50
  • 3.3 Instruction Formats

    50
    • 3.3.1 Memory Instruction Format

      51
      • 3.3.1.1 Memory Format Instructions with a Function Code

        51
      • 3.3.1.2 Memory Format Jump Instructions

        52
    • 3.3.2 Branch Instruction Format

      52
    • 3.3.3 Operate Instruction Format

      52
    • 3.3.4 Floating-Point Operate Instruction Format

      53
      • 3.3.4.1 Floating-Point Convert Instructions

        54
      • 3.3.4.2 Floating-Point/Integer Register Moves

        54
    • 3.3.5 PALcode Instruction Format

      54
• Instruction Descriptions

  57
  • 4.1 Instruction Set Overview

    57
    • 4.1.1 Subsetting Rules

      58
    • 4.1.2 Floating-Point Subsets

      58
    • 4.1.3 Software Emulation Rules

      59
    • 4.1.4 Opcode Qualifiers

      59
  • 4.2 Memory Integer Load/Store Instructions

    60
    • 4.2.1 Load Address

      61
    • 4.2.2 Load Memory Data into Integer Register

      62
    • 4.2.3 Load Unaligned Memory Data into Integer Register

      64
    • 4.2.4 Load Memory Data into Integer Register Locked

      65
    • 4.2.5 Store Integer Register Data into Memory Conditional

      68
    • 4.2.6 Store Integer Register Data into Memory

      71
    • 4.2.7 Store Unaligned Integer Register Data into Memory

      73
  • 4.3 Control Instructions

    74
    • 4.3.1 Conditional Branch

      76
    • 4.3.2 Unconditional Branch

      77
    • 4.3.3 Jumps

      78
  • 4.4 Integer Arithmetic Instructions

    80
    • 4.4.1 Longword Add

      81
    • 4.4.2 Scaled Longword Add

      82
    • 4.4.3 Quadword Add

      83
    • 4.4.4 Scaled Quadword Add

      84
    • 4.4.5 Integer Signed Compare

      85
    • 4.4.6 Integer Unsigned Compare

      86
    • 4.4.7 Count Leading Zero

      87
    • 4.4.8 Count Population

      88
    • 4.4.9 Count Trailing Zero

      89
    • 4.4.10 Longword Multiply

      90
    • 4.4.11 Quadword Multiply

      91
    • 4.4.12 Unsigned Quadword Multiply High

      92
    • 4.4.13 Longword Subtract

      93
    • 4.4.14 Scaled Longword Subtract

      94
    • 4.4.15 Quadword Subtract

      95
    • 4.4.16 Scaled Quadword Subtract

      96
  • 4.5 Logical and Shift Instructions

    97
    • 4.5.1 Logical Functions

      98
    • 4.5.2 Conditional Move Integer

      99
    • 4.5.3 Shift Logical

      101
    • 4.5.4 Shift Arithmetic

      102
  • 4.6 Byte Manipulation Instructions

    103
    • 4.6.1 Compare Byte

      105
    • 4.6.2 Extract Byte

      107
    • 4.6.3 Byte Insert

      111
    • 4.6.4 Byte Mask

      113
    • 4.6.5 Sign Extend

      116
    • 4.6.6 Zero Bytes

      117
  • 4.7 Floating-Point Instructions

    118
    • 4.7.1 Single-Precision Operations

      118
    • 4.7.2 Subsets and Faults

      118
    • 4.7.3 Definitions

      119
    • 4.7.4 Encodings

      121
    • 4.7.5 Rounding Modes

      122
    • 4.7.6 Computational Models

      123
      • 4.7.6.1 VAX-Format Arithmetic with Precise Exceptions

        123
      • 4.7.6.2 High-Performance VAX-Format Arithmetic

        124
      • 4.7.6.3 IEEE-Compliant Arithmetic

        124
      • 4.7.6.4 IEEE-Compliant Arithmetic Without Inexact Exception

        124
      • 4.7.6.5 High-Performance IEEE-Format Arithmetic

        125
    • 4.7.7 Trapping Modes

      125
      • 4.7.7.1 VAX Trapping Modes

        125
      • 4.7.7.2 IEEE Trapping Modes

        127
      • 4.7.7.3 Arithmetic Trap Completion

        129
        • 4.7.7.3.1 Trap Shadow Rules

          129
        • 4.7.7.3.2 Trap Shadow Length Rules

          130
      • 4.7.7.4 Invalid Operation (INV) Arithmetic Trap

        132
      • 4.7.7.5 Division by Zero (DZE) Arithmetic Trap

        133
      • 4.7.7.6 Overflow (OVF) Arithmetic Trap

        133
      • 4.7.7.7 Underflow (UNF) Arithmetic Trap

        134
      • 4.7.7.8 Inexact Result (INE) Arithmetic Trap

        134
      • 4.7.7.9 Integer Overflow (IOV) Arithmetic Trap

        134
      • 4.7.7.10 IEEE Floating-Point Trap Disable Bits

        134
      • 4.7.7.11 IEEE Denormal Control Bits

        135
    • 4.7.8 Floating-Point Control Register (FPCR)

      135
      • 4.7.8.1 Accessing the FPCR

        138
      • 4.7.8.2 Default Values of the FPCR

        139
      • 4.7.8.3 Saving and Restoring the FPCR

        139
    • 4.7.9 Floating-Point Instruction Function Field Format

      140
    • 4.7.10 IEEE Standard

      144
      • 4.7.10.1 Conversion of NaN and Infinity Values

        144
      • 4.7.10.2 Copying NaN Values

        145
      • 4.7.10.3 Generating NaN Values

        145
      • 4.7.10.4 Propagating NaN Values

        145
  • 4.8 Memory Format Floating-Point Instructions

    146
    • 4.8.1 Load F_floating

      147
    • 4.8.2 Load G_floating

      148
    • 4.8.3 Load S_floating

      149
    • 4.8.4 Load T_floating

      150
    • 4.8.5 Store F_floating

      151
    • 4.8.6 Store G_floating

      152
    • 4.8.7 Store S_floating

      153
    • 4.8.8 Store T_floating

      154
  • 4.9 Branch Format Floating-Point Instructions

    155
    • 4.9.1 Conditional Branch

      156
  • 4.10 Floating-Point Operate Format Instructions

    158
    • 4.10.1 Copy Sign

      161
    • 4.10.2 Convert Integer to Integer

      162
    • 4.10.3 Floating-Point Conditional Move

      163
    • 4.10.4 Move from/to Floating-Point Control Register

      165
    • 4.10.5 VAX Floating Add

      166
    • 4.10.6 IEEE Floating Add

      167
    • 4.10.7 VAX Floating Compare

      168
    • 4.10.8 IEEE Floating Compare

      169
    • 4.10.9 Convert VAX Floating to Integer

      170
    • 4.10.10 Convert Integer to VAX Floating

      171
    • 4.10.11 Convert VAX Floating to VAX Floating

      172
    • 4.10.12 Convert IEEE Floating to Integer

      173
    • 4.10.13 Convert Integer to IEEE Floating

      174
    • 4.10.14 Convert IEEE S_Floating to IEEE T_Floating

      175
    • 4.10.15 Convert IEEE T_Floating to IEEE S_Floating

      176
    • 4.10.16 VAX Floating Divide

      177
    • 4.10.17 IEEE Floating Divide

      178
    • 4.10.18 Floating-Point Register to Integer Register Move

      179
    • 4.10.19 Integer Register to Floating-Point Register Move

      180
    • 4.10.20 VAX Floating Multiply

      182
    • 4.10.21 IEEE Floating Multiply

      183
    • 4.10.22 VAX Floating Square Root

      184
    • 4.10.23 IEEE Floating Square Root

      185
    • 4.10.24 VAX Floating Subtract

      186
    • 4.10.25 IEEE Floating Subtract

      187
  • 4.11 Miscellaneous Instructions

    188
    • 4.11.1 Architecture Mask

      189
    • 4.11.2 Call Privileged Architecture Library

      191
    • 4.11.3 Evict Data Cache Block

      192
    • 4.11.4 Exception Barrier

      194
    • 4.11.5 Prefetch Data

      195
    • 4.11.6 Implementation Version

      197
    • 4.11.7 Memory Barrier

      198
    • 4.11.8 Read Processor Cycle Counter

      199
    • 4.11.9 Trap Barrier

      200
    • 4.11.10 Write Hint

      201
    • 4.11.11 Write Memory Barrier

      203
  • 4.12 VAX Compatibility Instructions

    205
    • 4.12.1 VAX Compatibility Instructions

      206
  • 4.13 Multimedia (Graphics and Video) Support

    207
    • 4.13.1 Byte and Word Minimum and Maximum

      208
    • 4.13.2 Pixel Error

      210
    • 4.13.3 Pack Bytes

      211
    • 4.13.4 Unpack Bytes

      212
• System Architecture and Programming Implications

  213
  • 5.1 Introduction

    213
  • 5.2 Physical Address Space Characteristics

    213
    • 5.2.1 Coherency of Memory Access

      213
    • 5.2.2 Granularity of Memory Access

      214
    • 5.2.3 Width of Memory Access

      215
    • 5.2.4 Memory-Like and Non-Memory-Like Behavior

      215
  • 5.3 Translation Buffers and Virtual Caches

    216
  • 5.4 Caches and Write Buffers

    216
  • 5.5 Data Sharing

    218
    • 5.5.1 Atomic Change of a Single Datum

      218
    • 5.5.2 Atomic Update of a Single Datum

      218
    • 5.5.3 Atomic Update of Data Structures

      219
    • 5.5.4 Ordering Considerations for Shared Data Structures

      221
  • 5.6 Read/Write Ordering

    222
    • 5.6.1 Alpha Shared Memory Model

      222
      • 5.6.1.1 Architectural Definition of Processor Issue Sequence

        224
      • 5.6.1.2 Definition of Before and After

        224
      • 5.6.1.3 Definition of Processor Issue Constraints

        224
      • 5.6.1.4 Definition of Location Access Constraints

        226
      • 5.6.1.5 Definition of Visibility

        226
      • 5.6.1.6 Definition of Storage

        226
      • 5.6.1.7 Definition of Dependence Constraint

        227
      • 5.6.1.8 Definition of Load-Locked and Store-Conditional

        228
      • 5.6.1.9 Timeliness

        229
    • 5.6.2 Litmus Tests

      229
      • 5.6.2.1 Litmus Test 1 (Impossible Sequence)

        229
      • 5.6.2.2 Litmus Test 2 (Impossible Sequence)

        230
      • 5.6.2.3 Litmus Test 3 (Impossible Sequence)

        230
      • 5.6.2.4 Litmus Test 4 (Sequence Okay)

        231
      • 5.6.2.5 Litmus Test 5 (Sequence Okay)

        231
      • 5.6.2.6 Litmus Test 6 (Sequence Okay)

        231
      • 5.6.2.7 Litmus Test 7 (Impossible Sequence)

        232
      • 5.6.2.8 Litmus Test 8 (Impossible Sequence)

        232
      • 5.6.2.9 Litmus Test 9 (Impossible Sequence)

        233
      • 5.6.2.10 Litmus Test 10 (Sequence Okay)

        233
      • 5.6.2.11 Litmus Test 11 (Impossible Sequence)

        233
    • 5.6.3 Implied Barriers

      234
    • 5.6.4 Implications for Software

      234
      • 5.6.4.1 Single Processor Data Stream

        234
      • 5.6.4.2 Single Processor Instruction Stream

        234
      • 5.6.4.3 Multiprocessor Data Stream (Including Single Processor with DMA I/O)

        234
      • 5.6.4.4 Multiprocessor Instruction Stream (Including Single Processor with DMA I/O)

        235
      • 5.6.4.5 Multiprocessor Context Switch

        236
      • 5.6.4.6 Multiprocessor Send/Receive Interrupt

        238
      • 5.6.4.7 Implications for Memory Mapped I/O

        239
      • 5.6.4.8 Multiple Processors Writing to a Single I/O Device

        240
    • 5.6.5 Implications for Hardware

      241
  • 5.7 Arithmetic Traps

    242
• Common PALcode Architecture

  243
  • 6.1 PALcode

    243
  • 6.2 PALcode Instructions and Functions

    243
  • 6.3 PALcode Environment

    244
  • 6.4 Special Functions Required for PALcode

    244
  • 6.5 PALcode Effects on System Code

    245
  • 6.6 PALcode Replacement

    245
  • 6.7 Required PALcode Instructions

    246
    • 6.7.1 Drain Aborts

      248
    • 6.7.2 Halt

      249
    • 6.7.3 Instruction Memory Barrier

      250
• Console Subsystem Overview

  251
• Input/Output Overview

  253
• OpenVMS Alpha

  255
  • 9.1 Unprivileged OpenVMS Alpha PALcode

    255
  • 9.2 Privileged OpenVMS Alpha Palcode

    262
• Digital UNIX

  265
  • 10.1 Unprivileged Digital UNIX PALcode

    265
  • 10.2 Privileged Digital UNIX PALcode

    266
• Windows NT Alpha

  269
  • 11.1 Unprivileged Windows NT Alpha PALcode

    269
  • 11.2 Privileged Windows NT Alpha PALcode

    270
• Software Considerations

  275
  • A.1 Hardware-Software Compact

    275
  • A.2 Instruction-Stream Considerations

    276
    • A.2.1 Instruction Alignment

      276
    • A.2.2 Branch Prediction and Minimizing Branch-Taken — Factor of 3

      276
    • A.2.3 Improving I-Stream Density — Factor of 3

      278
    • A.2.4 Instruction Scheduling — Factor of 3

      278
  • A.3 Data-Stream Considerations

    278
    • A.3.1 Data Alignment — Factor of 10

      278
    • A.3.2 Shared Data in Multiple Processors — Factor of 3

      279
    • A.3.3 Avoiding Cache/TB Conflicts — Factor of 1

      280
    • A.3.4 Sequential Read/Write — Factor of 1

      282
    • A.3.5 Prefetching — Factor of 3

      282
  • A.4 Code Sequences

    283
    • A.4.1 Aligned Byte/Word (Within Register) Memory Accesses

      283
    • A.4.2 Division

      284
    • A.4.3 Byte Swap

      285
    • A.4.4 Stylized Code Forms

      285
      • A.4.4.1 NOP

        285
      • A.4.4.2 Clear a Register

        286
      • A.4.4.3 Load Literal

        286
      • A.4.4.4 Register-to-Register Move

        287
      • A.4.4.5 Negate

        287
      • A.4.4.6 NOT

        287
      • A.4.4.7 Booleans

        287
    • A.4.5 Exceptions and Trap Barriers

      288
    • A.4.6 Pseudo-Operations (Stylized Code Forms)

      288
  • A.5 Timing Considerations: Atomic Sequences

    290
• IEEE Floating-Point Conformance

  291
  • B.1 Alpha Choices for IEEE Options

    291
  • B.2 Alpha Support for OS Completion Handlers

    293
    • B.2.1 IEEE Floating-Point Control (FP_C) Quadword

      294
  • B.3 Mapping to IEEE Standard

    296
• Instruction Summary

  303
  • C.1 Common Architecture Instruction Summary

    303
  • C.2 IEEE Floating-Point Instructions

    308
  • C.3 VAX Floating-Point Instructions

    309
  • C.4 Independent Floating-Point Instructions

    310
  • C.5 Opcode Summary

    310
  • C.6 Common Architecture Opcodes in Numerical Order

    312
  • C.7 OpenVMS Alpha PALcode Instruction Summary

    316
  • C.8 DIGITAL UNIX PALcode Instruction Summary

    318
  • C.9 Windows NT Alpha Instruction Summary

    319
  • C.10 PALcode Opcodes in Numerical Order

    320
  • C.11 Required PALcode Opcodes

    322
  • C.12 Opcodes Reserved to PALcode

    322
  • C.13 Opcodes Reserved to Compaq

    323
  • C.14 Unused Function Code Behavior

    323
  • C.15 ASCII Character Set

    324
• Registered System and Processor Identifiers

  325
  • D.1 Processor Type Assignments

    325
  • D.2 PALcode Variation Assignments

    326
  • D.3 Architecture Mask and Implementation Values

    327
• Waivers and Implementation-Dependent Functionality

  329
  • E.1 Waivers

    329
    • E.1.1 DECchip 21064, DECchip 21066, and DECchip 21068 IEEE Divide Instruction Violation

      329
    • E.1.2 DECchip 21064, DECchip 21066, and DECchip 21068 Write Buffer Violation

      330
    • E.1.3 DECchip 21264 LDx_L/STx_C with WH64 Violation

      330
  • E.2 Implementation-Specific Functionality

    331
    • E.2.1 DECchip 21064/21066/21068 Performance Monitoring

      331
      • E.2.1.1 DECchip 21064/21066/21068 Performance Monitor Interrupt Mechanism

        332
      • E.2.1.2 Functions and Arguments for the DECchip 21064/21066/21068

        333
    • E.2.2 DECchip 21164/21164PC Performance Monitoring

      337
      • E.2.2.1 Performance Monitor Interrupt Mechanism

        337
      • E.2.2.2 Windows NT Alpha Functions and Argument

        338
      • E.2.2.3 OpenVMS Alpha and DIGITAL UNIX Functions and Arguments

        340
    • E.2.3 21264 Performance Monitoring

      351
      • E.2.3.1 Performance Monitor Interrupt Mechanism

        351
      • E.2.3.2 Windows NT Alpha Functions and Argument

        352
      • E.2.3.3 OpenVMS Alpha and DIGITAL UNIX Functions and Arguments

        353
• Index

  359
  • A

    359
  • B

    360
  • C

    360
  • D

    361
  • E

    362
  • F

    362
  • G

    363
  • H

    363
  • I

    364
  • J

    365
  • L

    365
  • M

    366
  • N

    367
  • O

    367
  • P

    367
  • Q

    368
  • R

    368
  • S

    368
  • T

    369
  • U

    370
  • V

    370
  • W

    370
  • X

    370
  • Y

    371
  • Z

    371