Инструкции для Cypress CY7C0832BV

Содержание

• Features

  1
• Functional Description

  1
• Logic Block Diagram [2]

  2
• Pin Configurations

  3
• Pin Definitions

  5
• Byte Select Operation

  5
• Master Reset

  6
  • Mailbox Interrupts

    6
  • Address Counter and Mask Register Operations [16]

    6
  • Counter Reset Operation

    7
  • Counter Load Operation

    7
  • Counter Increment Operation

    7
  • Counter Hold Operation

    7
  • Counter Interrupt

    7
  • Counter Readback Operation

    7
  • Retransmit

    8
  • Mask Reset Operation

    8
  • Mask Load Operation

    8
  • Mask Readback Operation

    8
  • Counting by Two

    8
• IEEE 1149.1 Serial Boundary Scan (JTAG) [21]

  10
  • Performing a TAP Reset

    10
  • Performing a Pause/Restart

    10
  • Boundary Scan Hierarchy for 9-Mbit Device

    10
• Maximum Ratings

  12
• Operating Range

  12
• Electrical Characteristics

  12
• Capacitance

  12
• Switching Characteristics

  13
• JTAG Timing and Switching Waveforms

  15
• Switching Waveforms

  16
• Ordering Information

  24
  • 512K ° 18 (9M) 3.3V Synchronous CY7C0833AV Dual-Port SRAM

    24
  • 256K ° 18 (4M) 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM

    24
  • 128K ° 18 (2M) 3.3V Synchronous CY7C0831AV Dual-Port SRAM

    24
  • 64K ° 18 (1M) 3.3V Synchronous CY7C0830AV Dual-Port SRAM

    24
  • 32K ° 18 (512K) 3.3V Synchronous CY7C0837AV Dual-Port SRAM

    25
• Package Diagrams

  25
• Document History Page

  27
  • Sales, Solutions, and Legal Information

    28
  • Worldwide Sales and Design Support

    28
  • Products

    28
  • PSoC Solutions

    28