Справочник ПользователяСодержание1. Features (CY7C68013A/14A/15A/16A)11.1 Features (CY7C68013A/14A only)21.2 Features (CY7C68015A/16A only)22. Applications33. Functional Overview33.1 USB Signaling Speed33.2 8051 Microprocessor33.2.1 8051 Clock Frequency33.2.2 USARTS33.2.3 Special Function Registers33.3 I2C Bus33.4 Buses33.5 USB Boot Methods43.6 ReNumeration™43.7 Bus-powered Applications43.8 Interrupt System43.8.1 INT2 Interrupt Request and Enable Registers43.8.2 USB Interrupt Autovectors43.8.3 FIFO/GPIF Interrupt (INT4)53.9 Reset and Wakeup63.9.1 Reset Pin63.9.2 Wakeup Pins73.10 Program/Data RAM73.10.1 Size73.10.2 Internal Code Memory, EA = 073.10.3 External Code Memory, EA = 173.11 Register Addresses93.12 Endpoint RAM103.12.1 Size103.12.2 Organization103.12.3 Setup Data Buffer103.12.4 Endpoint Configurations (High -speed Mode)103.12.5 Default Full-Speed Alternate Settings113.12.6 Default High-Speed Alternate Settings113.13 External FIFO Interface113.13.1 Architecture113.13.2 Master/Slave Control Signals113.13.3 GPIF and FIFO Clock Rates123.14 GPIF123.14.1 Six Control OUT Signals123.14.2 Six Ready IN Signals123.14.3 Nine GPIF Address OUT Signals123.14.4 Long Transfer Mode123.15 ECC Generation[7]123.15.1 ECC Implementation123.16 USB Uploads and Downloads123.17 Autopointer Access123.18 I2C Controller133.18.1 I2C Port Pins133.18.2 I2C Interface Boot Load Access133.18.3 I2C Interface General-Purpose Access133.19 Compatible with Previous Generation EZ-USB FX2133.20 CY7C68013A/14A and CY7C68015A/16A Differences144. Pin Assignments144.1 CY7C68013A/15A Pin Descriptions215. Register Summary296. Absolute Maximum Ratings367. Operating Conditions368. Thermal Characteristics369. DC Characteristics379.1 USB Transceiver3710. AC Electrical Characteristics3710.1 USB Transceiver3710.2 Program Memory Read3810.3 Data Memory Read3910.4 Data Memory Write4010.5 PORTC Strobe Feature Timings4110.6 GPIF Synchronous Signals4210.7 Slave FIFO Synchronous Read4310.8 Slave FIFO Asynchronous Read4410.9 Slave FIFO Synchronous Write4510.10 Slave FIFO Asynchronous Write4610.11 Slave FIFO Synchronous Packet End Strobe4610.12 Slave FIFO Asynchronous Packet End Strobe4710.13 Slave FIFO Output Enable4810.14 Slave FIFO Address to Flags/Data4810.15 Slave FIFO Synchronous Address4910.16 Slave FIFO Asynchronous Address4910.17 Sequence Diagram5010.17.1 Single and Burst Synchronous Read Example5010.17.2 Single and Burst Synchronous Write5110.17.3 Sequence Diagram of a Single and Burst Asynchronous Read5210.17.4 Sequence Diagram of a Single and Burst Asynchronous Write5311. Ordering Information5412. Package Diagrams5513. PCB Layout Recommendations5914. Quad Flat Package No Leads (QFN) Package Design Notes60Logic Block Diagram2Logic Block Diagram2Размер: 1,7 МБСтраницы: 62Язык: EnglishПросмотреть