Справочник ПользователяСодержаниеS1C33L03 PRODUCT PART151 Outline171.1 Features171.2 Block Diagram191.3 Pin Description201.3.1 Pin Layout Diagram (plastic package)201.3.2 Pin Functions212 Power Supply282.1 Power Supply Pins282.2 Operating Voltage (VDD, VSS)282.3 Power Supply for I/O Interface (VDDE)292.4 Power Supply for Analog Circuits (AVDDE)293 Internal Memory303.1 ROM and Boot Address303.2 RAM314 Peripheral Circuits324.1 List of Peripheral Circuits324.2 I/O Memory Map335 Power-Down Control816 Basic External Wiring Diagram847 Precautions on Mounting858 Electrical Characteristics878.1 Absolute Maximum Rating878.2 Recommended Operating Conditions888.3 DC Characteristics898.4 Current Consumption918.5 A/D Converter Characteristics928.6 AC Characteristics948.6.1 Symbol Description948.6.2 AC Characteristics Measurement Condition948.6.3 C33 Block AC Characteristic Tables958.6.4 C33 Block AC Characteristic Timing Charts1038.6.5 LCD Interface AC Characteristics1128.7 Oscillation Characteristics1238.8 PLL Characteristics1249 Package1259.1 Plastic Package12510 Pad Layout12610.1 Pad Layout Diagram12610.2 Pad Coordinate127Appendix129A <Reference> External Device Interface Timings129A.1 DRAM (70ns)130A.2 DRAM (60ns)133A.3 ROM and Burst ROM137A.4 SRAM (55ns)139A.5 SRAM (70ns)141A.6 8255A143B Pin Characteristics144S1C33L03 FUNCTION PART147I OUTLINE149I-1 INTRODUCTION151I-2 BLOCK DIAGRAM153I-3 LIST OF PINS155List of External I/O Pins155II CORE BLOCK163II-1 INTRODUCTION165II-2 CPU AND OPERATING MODE167CPU167Standby Mode168HALT Mode168SLEEP Mode168Notes on Standby Mode169Test Mode169Debug Mode169Trap Table170II-3 INITIAL RESET173Pins for Initial Reset173Cold Start and Hot Start173Power-on Reset174Reset Pulse174Boot Address175Notes Related to Initial Reset175II-4 BCU (Bus Control Unit)177Pin Assignment for External System Interface177I/O Pin List177Combination of System Bus Control Signals179Memory Area180Memory Map180External Memory Map and Chip Enable181Using Internal Memory on External Memory Area183Exclusive Signals for Areas183Area 10184Area 3185Setting External Bus Conditions186Setting Device Type and Size186Setting SRAM Timing Conditions187Setting Timing Conditions of Burst ROM188Bus Operation189Data Arrangement in Memory189Bus Operation of External Memory189Bus Clock193Bus Speed Mode194Bus Clock Output194Bus Cycles in External System Interface195SRAM Read Cycles195Bus Timing196SRAM Write Cycles197Burst ROM Read Cycles199DRAM Direct Interface200Outline of DRAM Interface200DRAM Setting Conditions201DRAM Read/Write Cycles204DRAM Refresh Cycles207Releasing External Bus208Power-down Control by External Device209I/O Memory of BCU210II-5 ITC (Interrupt Controller)225Outline of Interrupt Functions225Maskable Interrupts225Interrupt Factors and Intelligent DMA227Nonmaskable Interrupt (NMI)227Interrupt Processing by the CPU227Clearing Standby Mode by Interrupts227Trap Table228Control of Maskable Interrupts229Structure of the Interrupt Controller229Processor Status Register (PSR)229Interrupt Factor Flag and Interrupt Enable Register230Interrupt Priority Register and Interrupt Levels232IDMA Invocation233HSDMA Invocation235I/O Memory of Interrupt Controller236Programming Notes249II-6 CLG (Clock Generator)251Configuration of Clock Generator251I/O Pins of Clock Generator252High-Speed (OSC3) Oscillation Circuit252PLL253Controlling Oscillation253Setting and Switching Over the CPU Operating Clock254Power-Control Register Protection Flag255Operation in Standby Mode255I/O Memory of Clock Generator256Programming Notes259II-7 DBG (Debug Unit)261Debug Circuit261I/O Pins of Debug Circuit261III PERIPHERAL BLOCK263III-1 INTRODUCTION265III-2 PRESCALER267Configuration of Prescaler267Source Clock267Selecting Division Ratio and Output Control for Prescaler268Source Clock Output to 8-Bit Programmable Timer268I/O Memory of Prescaler269Programming Notes274III-3 8-BIT PROGRAMMABLE TIMERS275Configuration of 8-Bit Programmable Timer275Output Pins of 8-Bit Programmable Timers275Uses of 8-Bit Programmable Timers276Control and Operation of 8-Bit Programmable Timer278Control of Clock Output2818-Bit Programmable Timer Interrupts and DMA282I/O Memory of 8-Bit Programmable Timers284Programming Notes291III-4 16-BIT PROGRAMMABLE TIMERS293Configuration of 16-Bit Programmable Timer293I/O Pins of 16-Bit Programmable Timers294Uses of 16-Bit Programmable Timers295Control and Operation of 16-Bit Programmable Timer296Controlling Clock Output29916-Bit Programmable Timer Interrupts and DMA301I/O Memory of 16-Bit Programmable Timers304Programming Notes317III-5 WATCHDOG TIMER319Configuration of Watchdog Timer319Control of Watchdog Timer319Operation in Standby Modes320I/O Memory of Watchdog Timer321Programming Notes321III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT323Configuration of Low-Speed (OSC1) Oscillation Circuit323I/O Pins of Low-Speed (OSC1) Oscillation Circuit323Oscillator Types324Controlling Oscillation325Switching Over the CPU Operating Clock325Power-Control Register Protection Flag326Operation in Standby Mode326OSC1 Clock Output to External Devices326I/O Memory of Low-Speed (OSC1) Oscillation Circuit327Programming Notes330III-7 CLOCK TIMER331Configuration of Clock Timer331Control and Operation of the Clock Timer332Interrupt Function334Examples of Use of Clock Timer336I/O Memory of Clock Timer337Programming Notes342III-8 SERIAL INTERFACE343Configuration of Serial Interfaces343Features of Serial Interfaces343I/O Pins of Serial Interface344Setting Transfer Mode345Clock-Synchronized Interface346Outline of Clock-Synchronized Interface346Setting Clock-Synchronized Interface347Control and Operation of Clock-Synchronized Transfer349Asynchronous Interface354Outline of Asynchronous Interface354Setting Asynchronous Interface355Control and Operation of Asynchronous Transfer358IrDA Interface363Outline of IrDA Interface363Setting IrDA Interface363Control and Operation of IrDA Interface365Serial Interface Interrupts and DMA366I/O Memory of Serial Interface370Programming Notes388III-9 INPUT/OUTPUT PORTS389Input Ports (K Ports)389Structure of Input Port389Input-Port Pins390Notes on Use390I/O Memory of Input Ports391I/O Ports (P Ports)392Structure of I/O Port392I/O Port Pins392I/O Control Register and I/O Modes393I/O Memory of I/O Ports394Input Interrupt400Port Input Interrupt400Key Input Interrupt402Control Registers of the Interrupt Controller404I/O Memory for Input Interrupts406Programming Notes413IV ANALOG BLOCK415IV-1 INTRODUCTION417IV-2 A/D CONVERTER419Features and Structure of A/D Converter419I/O Pins of A/D Converter420Setting A/D Converter421Control and Operation of A/D Conversion423A/D Converter Interrupt and DMA425I/O Memory of A/D Converter427Programming Notes433V DMA BLOCK435V-1 INTRODUCTION437V-2 HSDMA (High-Speed DMA)439Functional Outline of HSDMA439I/O Pins of HSDMA440Programming Control Information441Setting the Registers in Dual-Address Mode441Setting the Registers in Single-Address Mode444Enabling/Disabling DMA Transfer445Trigger Factor446Operation of HSDMA447Operation in Dual-Address Mode447Operation in Single-Address Mode450Timing Chart451Interrupt Function of HSDMA453I/O Memory of HSDMA455Programming Notes474V-3 IDMA (Intelligent DMA)475Functional Outline of IDMA475Programming Control Information475IDMA Invocation479Operation of IDMA482Linking486Interrupt Function of Intelligent DMA487I/O Memory of Intelligent DMA488Programming Notes491VI SDRAM CONTROLLER BLOCK493VI-1 INTRODUCTION495VI-2 SDRAM INTERFACE497Outline of SDRAM Interface497SDRAM Controller Block Diagram497I/O Pins and Connection498I/O Pins498Connection Examples498SDRAM Controller Configuration501Setting PLL501BCU Configuration501SDRAM Setting Conditions502SDRAM Operation508Synchronous Clock508Power-up and Initialization509SDRAM Commands510Burst Read Cycle511Single Read/Single Write512Refresh Mode513Power-down Mode515Bus Release Procedure515I/O Memory of SDRAM Interface517Programming Notes528Examples of SDRAM Controller Initialization Program529VII LCD CONTROLLER BLOCK531VII-1 INTRODUCTION533VII-2 LCD CONTROLLER535Overview535Features535Block Diagram537I/O Pins of the LCD Controller538System Settings539Setting the BCU539Display Memory539LCD Controller Setting Procedure540Clock541Setting the LCD Panel542Types of Panels542Resolution542Display Modes543Look-up Tables545Frame Rates553Other Settings554Display Control555Controlling LCD Power Up/Down555Reading/Writing Display Data556Setting the Display Start Address556Split-Screen Display557Virtual Screen and View Port557Inverting and Blanking the Display559Portrait Mode559Power Save563Controlling the GPIO Pins564I/O Memory of LCD Controller565Programming Notes576Precautions on Using ICD33576Examples of LCD Controller Setting Program577Appendix I/O MAP579Размер: 3,5 МБСтраницы: 631Язык: EnglishПросмотреть
