Инструкции для Freescale Semiconductor MCF51QE128RM

Содержание

• Chapter 1 Device Overview

  23
  • 1.1 Devices in the MCF51QE128/64/32 Series

    23
  • 1.2 MCU Block Diagram

    24
  • 1.3 V1 ColdFire Core

    26
  • 1.4 System Clocks

    26
    • 1.4.1 Internal Clock Source (ICS) Module

      26
    • 1.4.2 System Clock Distribution

      27
    • 1.4.3 ICS Modes of Operation

      29
• Chapter 2 Pins and Connections

  33
  • 2.1 Device Pin Assignment

    33
  • 2.2 Recommended System Connections

    35
    • 2.2.1 Power

      37
    • 2.2.2 Oscillator

      37
    • 2.2.3 RESET and RSTO

      37
    • 2.2.4 Background / Mode Select (BKGD/MS)

      38
    • 2.2.5 ADC Reference Pins (VREFH, VREFL)

      39
    • 2.2.6 General-Purpose I/O and Peripheral Ports

      39
• Chapter 3 Modes of Operation

  43
  • 3.1 Introduction

    43
  • 3.2 Features

    43
  • 3.3 Overview

    44
  • 3.4 Debug Mode

    48
  • 3.5 Secure Mode

    48
  • 3.6 Run Modes

    49
    • 3.6.1 Run Mode

      49
    • 3.6.2 Low-Power Run Mode (LPrun)

      49
  • 3.7 Wait Modes

    50
    • 3.7.1 Wait Mode

      50
    • 3.7.2 Low-Power Wait Mode (LPwait)

      50
  • 3.8 Stop Modes

    50
    • 3.8.1 Stop2 Mode

      51
    • 3.8.2 Stop3 Mode

      52
    • 3.8.3 Stop4: Low Voltage Detect or BDM Enabled in Stop Mode

      52
  • 3.9 On-Chip Peripheral Modules in Stop and Low-Power Modes

    53
• Chapter 4 Memory

  57
  • 4.1 MCF51QE128/64/32 Memory Map

    57
  • 4.2 Register Addresses and Bit Assignments

    58
    • 4.2.1 Flash Module Reserved Memory Locations

      67
    • 4.2.2 ColdFire Rapid GPIO Memory Map

      69
    • 4.2.3 ColdFire Interrupt Controller Memory Map

      69
  • 4.3 RAM

    70
  • 4.4 Flash

    70
    • 4.4.1 Features

      71
    • 4.4.2 Register Descriptions

      72
  • 4.5 Function Description

    77
    • 4.5.1 Flash Command Operations

      77
    • 4.5.2 Flash Commands

      80
    • 4.5.3 Illegal Flash Operations

      87
    • 4.5.4 Operating Modes

      88
    • 4.5.5 Security

      89
    • 4.5.6 Resets

      90
  • 4.6 Security

    91
• Chapter 5 Resets, Interrupts, and General System Control

  93
  • 5.1 Introduction

    93
  • 5.2 Features

    93
  • 5.3 Microcontroller Reset

    93
    • 5.3.1 Computer Operating Properly (COP) Watchdog

      94
    • 5.3.2 Illegal Operation Reset

      95
    • 5.3.3 Illegal Address Reset

      95
  • 5.4 Interrupts and Exceptions

    95
    • 5.4.1 External Interrupt Request (IRQ) Pin

      95
  • 5.5 Low-Voltage Detect (LVD) System

    96
    • 5.5.1 Power-On Reset Operation

      96
    • 5.5.2 LVD Reset Operation

      97
    • 5.5.3 LVD Interrupt Operation

      97
    • 5.5.4 Low-Voltage Warning (LVW) Interrupt Operation

      97
  • 5.6 Peripheral Clock Gating

    97
  • 5.7 Reset, Interrupt, and System Control Registers and Control Bits

    97
    • 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)

      98
    • 5.7.2 System Reset Status Register (SRS)

      99
    • 5.7.3 System Options Register 1 (SOPT1)

      100
    • 5.7.4 System Options Register 2 (SOPT2)

      101
    • 5.7.5 System Device Identification Register (SDIDH, SDIDL)

      102
    • 5.7.6 System Power Management Status and Control 1 Register (SPMSC1)

      103
    • 5.7.7 System Power Management Status and Control 2 Register (SPMSC2)

      104
    • 5.7.8 System Power Management Status and Control 3 Register (SPMSC3)

      105
    • 5.7.9 System Clock Gating Control 1 Register (SCGC1)

      107
    • 5.7.10 System Clock Gating Control 2 Register (SCGC2)

      107
• Chapter 6 Parallel Input/Output Control

  113
  • 6.1 Port Data and Data Direction

    113
  • 6.2 Pull-up, Slew Rate, and Drive Strength

    114
    • 6.2.1 Port Internal Pull-up Enable

      114
    • 6.2.2 Port Slew Rate Enable

      114
    • 6.2.3 Port Drive Strength Select

      115
  • 6.3 Port Data Set, Clear and Toggle Data Registers

    115
    • 6.3.1 Port Data Set Registers

      116
    • 6.3.2 Port Data Clear Registers

      116
    • 6.3.3 Port Data Toggle Register

      116
  • 6.4 V1 ColdFire Rapid GPIO Functionality

    116
  • 6.5 Keyboard Interrupts

    116
    • 6.5.1 Edge Only Sensitivity

      117
    • 6.5.2 Edge and Level Sensitivity

      117
    • 6.5.3 Pull-up/Pull-down Resistors

      117
    • 6.5.4 Keyboard Interrupt Initialization

      118
  • 6.6 Pin Behavior in Stop Modes

    118
  • 6.7 Parallel I/O, Keyboard Interrupt, and Pin Control Registers

    118
    • 6.7.1 Port A Registers

      118
    • 6.7.2 Port B Registers

      121
    • 6.7.3 Port C Registers

      123
    • 6.7.4 Port D Registers

      126
    • 6.7.5 Port E Registers

      128
    • 6.7.6 Port F Registers

      132
    • 6.7.7 Port G Registers

      134
    • 6.7.8 Port H Registers

      136
    • 6.7.9 Port J Registers

      138
    • 6.7.10 Keyboard Interrupt 1 (KBI1) Registers

      140
    • 6.7.11 Keyboard Interrupt 1 (KBI2) Registers

      141
• Chapter 7 ColdFire Core

  145
  • 7.1 Introduction

    145
    • 7.1.1 Overview

      145
  • 7.2 Memory Map/Register Description

    146
    • 7.2.1 Data Registers (D0-D7)

      147
    • 7.2.2 Address Registers (A0-A6)

      148
    • 7.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)

      148
    • 7.2.4 Condition Code Register (CCR)

      149
    • 7.2.5 Program Counter (PC)

      150
    • 7.2.6 Vector Base Register (VBR)

      150
    • 7.2.7 CPU Configuration Register (CPUCR)

      151
    • 7.2.8 Status Register (SR)

      152
  • 7.3 Functional Description

    153
    • 7.3.1 Instruction Set Architecture (ISA_C)

      153
    • 7.3.2 Exception Processing Overview

      154
    • 7.3.3 Processor Exceptions

      159
    • 7.3.4 Instruction Execution Timing

      167
• Chapter 8 Interrupt Controller (CF1_INTC)

  173
  • 8.1 Introduction

    173
    • 8.1.1 Overview

      174
    • 8.1.2 Features

      177
    • 8.1.3 Modes of Operation

      178
  • 8.2 External Signal Description

    178
  • 8.3 Memory Map and Register Definition

    178
    • 8.3.1 Memory Map

      179
    • 8.3.2 Register Descriptions

      179
    • 8.3.3 Interrupt Request Level and Priority Assignments

      185
  • 8.4 Functional Description

    187
    • 8.4.1 Handling of Non-Maskable Level 7 Interrupt Requests

      187
  • 8.5 Initialization Information

    188
  • 8.6 Application Information

    188
    • 8.6.1 Emulation of the HCS08’s 1-Level IRQ Handling

      188
    • 8.6.2 Using INTC_PL6P{7,6} Registers

      189
    • 8.6.3 More on Software IACKs

      189
• Chapter 9 Rapid GPIO (RGPIO)

  193
  • 9.1 Introduction

    193
    • 9.1.1 Overview

      195
    • 9.1.2 Features

      197
    • 9.1.3 Modes of Operation

      198
  • 9.2 External Signal Description

    198
    • 9.2.1 Overview

      198
    • 9.2.2 Detailed Signal Descriptions

      198
  • 9.3 Memory Map/Register Definition

    199
    • 9.3.1 Memory Map

      199
    • 9.3.2 Register Descriptions

      200
  • 9.4 Functional Description

    203
  • 9.5 Initialization Information

    203
  • 9.6 Application Information

    203
    • 9.6.1 Application 1: Simple Square-Wave Generation

      203
    • 9.6.2 Application 2: 16-bit Message Transmission using SPI Protocol

      204
• Chapter 10 Analog Comparator 3V (ACMPVLPV1)

  207
  • 10.1 Introduction

    207
    • 10.1.1 ACMP Configuration Information

      207
    • 10.1.2 ACMP/TPM Configuration Information

      207
    • 10.1.3 ACMP Clock Gating

      207
    • 10.1.4 Interrupt Vectors

      208
    • 10.1.5 Features

      211
    • 10.1.6 Modes of Operation

      211
    • 10.1.7 Block Diagram

      211
  • 10.2 External Signal Description

    212
  • 10.3 Register Definition

    212
    • 10.3.1 Status and Control Register (ACMPxSC)

      212
  • 10.4 Functional Description

    213
  • 10.5 Interrupts

    213
• Chapter 11 Analog-to-Digital Converter (S08ADC12V1)

  215
  • 11.1 Introduction

    215
    • 11.1.1 ADC Clock Gating

      215
    • 11.1.2 Module Configurations

      217
    • 11.1.3 Interrupt Vectors

      218
    • 11.1.4 Features

      219
    • 11.1.5 Block Diagram

      219
  • 11.2 External Signal Description

    220
    • 11.2.1 Analog Power (VDDAD)

      221
    • 11.2.2 Analog Ground (VSSAD)

      221
    • 11.2.3 Voltage Reference High (VREFH)

      221
    • 11.2.4 Voltage Reference Low (VREFL)

      221
    • 11.2.5 Analog Channel Inputs (ADx)

      221
  • 11.3 Register Definition

    221
    • 11.3.1 Status and Control Register 1 (ADCSC1)

      221
    • 11.3.2 Status and Control Register 2 (ADCSC2)

      223
    • 11.3.3 Data Result High Register (ADCRH)

      223
    • 11.3.4 Data Result Low Register (ADCRL)

      224
    • 11.3.5 Compare Value High Register (ADCCVH)

      224
    • 11.3.6 Compare Value Low Register (ADCCVL)

      225
    • 11.3.7 Configuration Register (ADCCFG)

      225
    • 11.3.8 Pin Control 1 Register (APCTL1)

      226
    • 11.3.9 Pin Control 2 Register (APCTL2)

      227
    • 11.3.10 Pin Control 3 Register (APCTL3)

      228
  • 11.4 Functional Description

    229
    • 11.4.1 Clock Select and Divide Control

      230
    • 11.4.2 Input Select and Pin Control

      230
    • 11.4.3 Hardware Trigger

      230
    • 11.4.4 Conversion Control

      230
    • 11.4.5 Automatic Compare Function

      233
    • 11.4.6 MCU Wait Mode Operation

      233
    • 11.4.7 MCU Stop3 Mode Operation

      234
    • 11.4.8 MCU Stop2 Mode Operation

      234
  • 11.5 Initialization Information

    234
    • 11.5.1 ADC Module Initialization Example

      235
  • 11.6 Application Information

    236
    • 11.6.1 External Pins and Routing

      236
    • 11.6.2 Sources of Error

      238
• Chapter 12 Internal Clock Source (S08ICSV3)

  243
  • 12.1 Introduction

    243
    • 12.1.1 External Oscillator

      243
    • 12.1.2 Stop2 Mode Considerations

      243
    • 12.1.3 Features

      247
    • 12.1.4 Block Diagram

      248
    • 12.1.5 Modes of Operation

      248
  • 12.2 External Signal Description

    249
  • 12.3 Register Definition

    249
    • 12.3.1 ICS Control Register 1 (ICSC1)

      250
    • 12.3.2 ICS Control Register 2 (ICSC2)

      251
    • 12.3.3 ICS Trim Register (ICSTRM)

      251
    • 12.3.4 ICS Status and Control (ICSSC)

      252
  • 12.4 Functional Description

    254
    • 12.4.1 Operational Modes

      254
    • 12.4.2 Mode Switching

      256
    • 12.4.3 Bus Frequency Divider

      256
    • 12.4.4 Low Power Bit Usage

      257
    • 12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator

      257
    • 12.4.6 Internal Reference Clock

      257
    • 12.4.7 External Reference Clock

      257
    • 12.4.8 Fixed Frequency Clock

      258
    • 12.4.9 The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source. ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency to be valid. Local Clock

      258
• Chapter 13 Inter-Integrated Circuit (S08IICV2)

  259
  • 13.1 Introduction

    259
    • 13.1.1 Module Configuration

      259
    • 13.1.2 Interrupt Vectors

      259
    • 13.1.3 Features

      262
    • 13.1.4 Modes of Operation

      262
    • 13.1.5 Block Diagram

      263
  • 13.2 External Signal Description

    263
    • 13.2.1 SCL - Serial Clock Line

      263
    • 13.2.2 SDA - Serial Data Line

      263
  • 13.3 Register Definition

    263
    • 13.3.1 IIC Address Register (IICA)

      264
    • 13.3.2 IIC Frequency Divider Register (IICF)

      264
    • 13.3.3 IIC Control Register (IICC1)

      267
    • 13.3.4 IIC Status Register (IICS)

      268
    • 13.3.5 IIC Data I/O Register (IICD)

      269
    • 13.3.6 IIC Control Register 2 (IICC2)

      269
  • 13.4 Functional Description

    270
    • 13.4.1 IIC Protocol

      270
    • 13.4.2 10-bit Address

      274
    • 13.4.3 General Call Address

      275
  • 13.5 Resets

    275
  • 13.6 Interrupts

    275
    • 13.6.1 Byte Transfer Interrupt

      275
    • 13.6.2 Address Detect Interrupt

      275
    • 13.6.3 Arbitration Lost Interrupt

      275
  • 13.7 Initialization/Application Information

    277
• Chapter 14 Real-Time Counter (S08RTCV1)

  281
  • 14.1 Introduction

    281
    • 14.1.1 ADC Hardware Trigger

      281
    • 14.1.2 RTC Clock Sources

      281
    • 14.1.3 RTC Modes of Operation

      281
    • 14.1.4 RTC Clock Gating

      281
    • 14.1.5 Interrupt Vector

      282
    • 14.1.6 Features

      284
    • 14.1.7 Modes of Operation

      284
    • 14.1.8 Block Diagram

      285
  • 14.2 External Signal Description

    285
  • 14.3 Register Definition

    285
    • 14.3.1 RTC Status and Control Register (RTCSC)

      286
    • 14.3.2 RTC Counter Register (RTCCNT)

      287
    • 14.3.3 RTC Modulo Register (RTCMOD)

      287
  • 14.4 Functional Description

    287
    • 14.4.1 RTC Operation Example

      288
  • 14.5 Initialization/Application Information

    289
• Chapter 15 Serial Communications Interface (S08SCIV4)

  291
  • 15.1 Introduction

    291
    • 15.1.1 SCI Clock Gating

      291
    • 15.1.2 Interrupt Vectors

      291
    • 15.1.3 Features

      295
    • 15.1.4 Modes of Operation

      295
    • 15.1.5 Block Diagram

      296
  • 15.2 Register Definition

    298
    • 15.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL)

      298
    • 15.2.2 SCI Control Register 1 (SCIxC1)

      299
    • 15.2.3 SCI Control Register 2 (SCIxC2)

      300
    • 15.2.4 SCI Status Register 1 (SCIxS1)

      301
    • 15.2.5 SCI Status Register 2 (SCIxS2)

      303
    • 15.2.6 SCI Control Register 3 (SCIxC3)

      304
    • 15.2.7 SCI Data Register (SCIxD)

      305
  • 15.3 Functional Description

    305
    • 15.3.1 Baud Rate Generation

      305
    • 15.3.2 Transmitter Functional Description

      306
    • 15.3.3 Receiver Functional Description

      307
    • 15.3.4 Interrupts and Status Flags

      309
    • 15.3.5 Additional SCI Functions

      310
• Chapter 16 Serial Peripheral Interface (S08SPIV3)

  313
  • 16.1 Introduction

    313
    • 16.1.1 SPI Clock Gating

      313
    • 16.1.2 Interrupt Vector

      313
    • 16.1.3 Features

      317
    • 16.1.4 Block Diagrams

      317
    • 16.1.5 SPI Baud Rate Generation

      319
  • 16.2 External Signal Description

    320
    • 16.2.1 SPSCK - SPI Serial Clock

      320
    • 16.2.2 MOSI - Master Data Out, Slave Data In

      320
    • 16.2.3 MISO - Master Data In, Slave Data Out

      320
    • 16.2.4 SS - Slave Select

      320
  • 16.3 Modes of Operation

    321
    • 16.3.1 SPI in Stop Modes

      321
  • 16.4 Register Definition

    321
    • 16.4.1 SPI Control Register 1 (SPIxC1)

      321
    • 16.4.2 SPI Control Register 2 (SPIxC2)

      322
    • 16.4.3 SPI Baud Rate Register (SPIxBR)

      323
    • 16.4.4 SPI Status Register (SPIxS)

      324
    • 16.4.5 SPI Data Register (SPIxD)

      325
  • 16.5 Functional Description

    325
    • 16.5.1 SPI Clock Formats

      326
    • 16.5.2 SPI Interrupts

      328
    • 16.5.3 Mode Fault Detection

      329
• Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3)

  331
  • 17.1 Introduction

    331
    • 17.1.1 ACMP/TPM Configuration Information

      331
    • 17.1.2 TPM Clock Gating

      331
    • 17.1.3 Interrupt Vector

      331
    • 17.1.4 Features

      335
    • 17.1.5 Modes of Operation

      335
    • 17.1.6 Block Diagram

      336
  • 17.2 Signal Description

    338
    • 17.2.1 Detailed Signal Descriptions

      338
  • 17.3 Register Definition

    341
    • 17.3.1 TPM Status and Control Register (TPMxSC)

      341
    • 17.3.2 TPM Counter Registers (TPMxCNTH:TPMxCNTL)

      342
    • 17.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)

      343
    • 17.3.4 TPM Channel n Status and Control Register (TPMxCnSC)

      344
    • 17.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)

      346
  • 17.4 Functional Description

    347
    • 17.4.1 Counter

      347
    • 17.4.2 Channel Mode Selection

      349
  • 17.5 Reset Overview

    352
    • 17.5.1 General

      352
    • 17.5.2 Description of Reset Operation

      352
  • 17.6 Interrupts

    352
    • 17.6.1 General

      352
    • 17.6.2 Description of Interrupt Operation

      353
• Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

  355
  • 18.1 Introduction

    355
    • 18.1.1 Overview

      356
    • 18.1.2 Features

      357
    • 18.1.3 Modes of Operations

      357
  • 18.2 External Signal Descriptions

    359
  • 18.3 Memory Map/Register Definition

    360
    • 18.3.1 Configuration/Status Register (CSR)

      361
    • 18.3.2 Extended Configuration/Status Register (XCSR)

      364
    • 18.3.3 Configuration/Status Register 2 (CSR2)

      367
    • 18.3.4 Configuration/Status Register 3 (CSR3)

      370
    • 18.3.5 BDM Address Attribute Register (BAAR)

      371
    • 18.3.6 Address Attribute Trigger Register (AATR)

      372
    • 18.3.7 Trigger Definition Register (TDR)

      373
    • 18.3.8 Program Counter Breakpoint/Mask Registers (PBR0-3, PBMR)

      376
    • 18.3.9 Address Breakpoint Registers (ABLR, ABHR)

      378
    • 18.3.10 Data Breakpoint and Mask Registers (DBR, DBMR)

      379
    • 18.3.11 Resulting Set of Possible Trigger Combinations

      380
  • 18.4 Functional Description

    380
    • 18.4.1 Background Debug Mode (BDM)

      380
    • 18.4.2 Real-Time Debug Support

      409
    • 18.4.3 Real-Time Trace Support

      409
    • 18.4.4 Freescale-Recommended BDM Pinout

      419
  • Appendix A Revision History

    421
  • A.1 Changes between Rev. 2 and Rev. 3

    421