Справочник ПользователяСодержаниеMPC5200B Users Guide1Chapter 1 Introduction361.1 Overview361.1.1 Features361.2 Architecture371.2.1 Embedded e300 Core401.2.2 BestComm I / O Subsystem411.2.2.1 Programmable Serial Controllers ( PSCs )411.2.2.2 10 / 100 Ethernet Controller411.2.2.3 Universal Serial Bus ( USB )411.2.2.4 Infrared Support411.2.2.5 Inter-Integrated Circuit ( I 2 C )411.2.2.6 Serial Peripheral Interface ( SPI )411.2.3 Controller Area Network ( CAN )411.2.4 Byte Data Link Controller - Digital BDLC-D421.2.5 System Level Interfaces421.2.5.1 Chip Selects421.2.5.2 Interrupt Controller421.2.5.3 Timers421.2.5.4 General Purpose Input / Outputs ( GPIO )421.2.5.5 Functional Pin Multiplexing431.2.5.6 Real-Time Clock ( RTC )431.2.6 SDRAM Controller and Interface431.2.7 Multi-Function External LocalPlus Bus431.2.8 Power Management431.2.9 Systems Debug and Test441.2.10 Physical Characteristics44Chapter 2 Signal Descriptions462.1 Overview462.2 Pinout Tables49Chapter 3 Memory Map1203.1 Overview1203.2 Internal Register Memory Map1213.3 MPC5200B Memory Map1223.3.1 MPC5200B Internal Register Space1223.3.2 External Busses1223.3.2.1 SDRAM Bus1223.3.2.2 LocalPlus Bus1233.3.3 Memory Map Space Register Description1243.3.3.1 Memory Address Base Register -MBAR + 0x00001243.3.3.2 Boot and Chip Select Addresses1243.3.3.3 SDRAM Chip Select Configuration Registers1253.3.3.4 IPBI Control Register and Wait State Enable -MBAR+0x0054127Chapter 4 Resets and Reset Configuration1284.1 Overview1284.2 Hard and Soft Reset Pins1284.2.1 Power-On Reset-PORRESET1284.2.2 Hard Reset-HRESET1284.2.3 Soft Reset-SRESET1294.3 Reset Sequence1294.4 Reset Operation1294.5 Other Resets1304.6 Reset Configuration131Chapter 5 Clocks and Power Management1345.1 Overview1345.2 Clock Distribution Module (CDM)1345.3 MPC5200B Clock Domains1345.3.1 MPC5200B Top Level Clock Relations1365.3.2 e300 Core Clock Domain1385.3.3 Processor Bus (XLB ) Clock Domain1405.3.4 SDRAM Memory Controller Clock Domain1405.3.5 IPB Clock Domain1415.3.6 PCI Clock Domain1415.4 Power Management1425.4.1 Full-Power Mode1425.4.2 Power Conservation Modes1425.4.3 e300 Core Power Modes1425.4.3.1 Dynamic Power Mode1435.4.3.2 Doze Mode1435.4.3.3 Nap Mode1435.4.3.4 Sleep Mode1435.4.4 Deep-Sleep Mode1435.4.4.1 Entering Deep Sleep1445.4.4.2 Exiting Deep Sleep1445.5 CDM Registers1445.5.1 CDM JTAG ID Number Register-MBAR + 0x02001455.5.2 CDM Power On Reset Configuration Register-MBAR + 0x02041455.5.3 CDM Bread Crumb Register-MBAR + 0x02081475.5.4 CDM Configuration Register-MBAR + 0x020C1475.5.5 CDM 48MHz Fractional Divider Configuration Register-MBAR + 0x02101485.5.6 CDM Clock Enable Register-MBAR + 0x02141495.5.7 CDM System Oscillator Configuration Register-MBAR + 0x02181505.5.8 CDM Clock Control Sequencer Configuration Register-MBAR + 0x021C1515.5.9 CDM Soft Reset Register-MBAR + 0x02201535.5.10 CDM System PLL Status Register-MBAR + 0x02241535.5.11 PSC1 Mclock Config Register-MBAR + 0x02281545.5.12 PSC2 Mclock Config Register-MBAR + 0x022C1555.5.13 PSC3 Mclock Config Register-MBAR + 0x02301555.5.14 PSC6 (IrDA) Mclock Config Register-MBAR + 0x0234156Chapter 6 e300 Processor Core1586.1 Overview1586.2 MPC5200B e300 Processor Core Functional Overview1586.3 e300 Core Reference Manual1596.4 Not supported e300 Core Features1596.4.1 Not supported instruction1596.4.2 Not supported XLB parity feature159Chapter 7 System Integration Unit ( SIU )1607.1 Overview1607.2 Interrupt Controller1607.2.1 Block Description1607.2.1.1 Machine Check Pin-core_mcp1617.2.1.2 System Management Interrupt-core_smi1617.2.1.3 Standard Interrupt-core_int1617.2.2 Interface Description1637.2.3 Programming Note1637.2.4 Interrupt Controller Registers1647.2.4.1 ICTL Peripheral Interrupt Mask Register-MBAR + 0x05001647.2.4.2 ICTL Peripheral Priority and HI / LO Select 1 Register -MBAR + 0x05041667.2.4.3 ICTL Peripheral Priority and HI / LO Select 2 Register -MBAR + 0x05081677.2.4.4 ICTL Peripheral Priority and HI / LO Select 3 Register -MBAR + 0x050C1677.2.4.5 ICTL External Enable and External Types Register -MBAR + 0x05101687.2.4.6 ICTL Critical Priority and Main Interrupt Mask Register-MBAR + 0x05141697.2.4.7 ICTL Main Interrupt Priority and INT / SMI Select 1 Register -MBAR + 0x05181717.2.4.8 ICTL Main Interrupt Priority and INT / SMI Select 2 Register-MBAR + 0x051C1727.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register-MBAR + 0x05241737.2.4.10 ICTL Critical Interrupt Status All Register-MBAR + 0x05281747.2.4.11 ICTL Main Interrupt Status All Register-MBAR + 0x052C1757.2.4.12 ICTL Peripheral Interrupt Status All Register-MBAR + 0x05301767.2.4.13 ICTL Peripheral Interrupt Status All Register-MBAR + 0x05381777.2.4.14 ICTL Main Interrupt Emulation All Register-MBAR + 0x05401787.2.4.15 ICTL Peripheral Interrupt Emulation All Register-MBAR + 0x05441797.2.4.16 ICTL IRQ Interrupt Emulation All Register-MBAR + 0x05481807.3 General Purpose I / O ( GPIO )1817.3.1 GPIO Pin Multiplexing1847.3.1.1 PSC1 ( UART1 / AC97 / CODEC1 )1857.3.1.2 PSC2 ( CAN1/2/UART2 / AC97 / CODEC2 )1857.3.1.3 PSC3 ( USB2 / CODEC3 / SPI / UART3 )1857.3.1.4 USB1/ RST_CONFIG1857.3.1.5 Ethernet / USB2 /UART4/5/J1850/ RST_CONFIG1857.3.1.6 PSC61867.3.1.7 I2C1867.3.1.8 GPIO Timer Pins1867.3.1.9 Dedicated GPIO Port1877.3.2 GPIO Programmer’s Model1877.3.2.1 GPIO Standard Registers-MBAR + 0x0B001877.3.2.1.1 GPS Port Configuration Register-MBAR + 0x0B001887.3.2.1.2 GPS Simple GPIO Enables Register-MBAR + 0x0B041907.3.2.1.3 GPS Simple GPIO Open Drain Type Register -MBAR + 0x0B081927.3.2.1.4 GPS Simple GPIO Data Direction Register-MBAR + 0x0B0C1937.3.2.1.5 GPS Simple GPIO Data Output Values Register -MBAR + 0x0B101967.3.2.1.6 GPS Simple GPIO Data Input Values Register -MBAR + 0x0B141977.3.2.1.7 GPS GPIO Output-Only Enables Register -MBAR + 0x0B181987.3.2.1.8 GPS GPIO Output-Only Data Value Out Register -MBAR + 0x0B1C1997.3.2.1.9 GPS GPIO Simple Interrupt Enable Register-MBAR + 0x0B202007.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register -MBAR + 0x0B242017.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register -MBAR + 0x0B282027.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register -MBAR + 0x0B2C2027.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register -MBAR + 0x0B302037.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register -MBAR + 0x0B342047.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register -MBAR + 0x0B382047.3.2.1.16 GPS GPIO Simple Interrupt Status Register-MBAR + 0x0B3C2057.3.2.2 WakeUp GPIO Registers-MBAR + 0x0C002067.3.2.2.1 GPW WakeUp GPIO Enables Register-MBAR + 0x0C002067.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register -MBAR + 0x0C042077.3.2.2.3 GPW WakeUp GPIO Data Direction Register-MBAR + 0x0C082077.3.2.2.4 GPW WakeUp GPIO Data Value Out Register -MBAR + 0x0C0C2087.3.2.2.5 GPW WakeUp GPIO Interrupt Enable Register-MBAR + 0x0C102097.3.2.2.6 GPW WakeUp GPIO Individual Interrupt Enable Register -MBAR + 0x0C142097.3.2.2.7 GPW WakeUp GPIO Interrupt Types Register-MBAR + 0x0C182107.3.2.2.8 GPW WakeUp GPIO Master Enables Register -MBAR + 0x0C1C2117.3.2.2.9 GPW WakeUp GPIO Data Input Values Register -MBAR + 0x0C202127.3.2.2.10 GPW WakeUp GPIO Status Register-MBAR + 0x0C242137.4 General Purpose Timers ( GPT )2147.4.1 Timer Configuration Method2147.4.2 Mode Overview2147.4.3 Programming Notes2147.4.4 GPT Registers-MBAR + 0x06002157.4.4.1 GPT 0 Enable and Mode Select Register-MBAR + 0x06002157.4.4.2 GPT 0 Counter Input Register-MBAR + 0x06042187.4.4.3 GPT 0 PWM Configuration Register-MBAR + 0x06082197.4.4.4 GPT 0 Status Register-MBAR + 0x060C2207.5 Slice Timers2217.5.1 SLT Registers-MBAR + 0x07002217.5.1.1 SLT 0 Terminal Count Register-MBAR + 0x07002227.5.1.2 SLT 0 Control Register-MBAR + 0x07042227.5.1.3 SLT 0 Count Value Register-MBAR + 0x07082237.5.1.4 SLT 0 Timer Status Register-MBAR + 0x070C2247.6 Real-Time Clock2247.6.1 Real-Time Clock Signals2257.6.2 Programming Note2257.6.3 RTC Interface Registers-MBAR + 0x08002257.6.3.1 RTC Time Set Register-MBAR + 0x08002267.6.3.2 RTC Date Set Register-MBAR + 0x08042277.6.3.3 RTC New Year and Stopwatch Register-MBAR + 0x08082287.6.3.4 RTC Alarm and Interrupt Enable Register-MBAR + 0x080C2287.6.3.5 RTC Current Time Register-MBAR + 0x08102297.6.3.6 RTC Current Date Register-MBAR + 0x08142307.6.3.7 RTC Alarm and Stopwatch Interrupt Register-MBAR + 0x08182307.6.3.8 RTC Periodic Interrupt and Bus Error Register-MBAR + 0x081C2317.6.3.9 RTC Test Register/Divides Register-MBAR + 0x0820232Chapter 8 SDRAM Memory Controller2348.1 Overview2348.2 Terminology and Notation2348.2.1 “Endian”-ness2348.3 Features2358.3.1 Devices Supported2368.4 Functional Description2488.4.1 External Signals (SDRAM Side)2488.4.2 Block Diagram2498.4.3 Transfer Size2498.4.4 Commands2508.4.4.1 Load Mode/Extended Mode Register Command2508.4.4.2 Precharge All Banks Command2518.4.4.3 Row and Bank Active Command2518.4.4.4 Read Command2518.4.4.5 Write Command2518.4.4.6 Burst Terminate Command2528.4.4.7 Auto Refresh Command2528.4.4.8 Self Refresh and Power Down Commands2528.5 Operation2528.5.1 Power-Up Initialization2528.5.2 Read Clock2538.6 Programming the SDRAM Controller2538.7 Memory Controller Registers (MBAR+0x0100:0x010C)2538.7.1 Mode Register-MBAR + 0x01002538.7.2 Control Register-MBAR + 0x01042558.7.3 Configuration Register 1-MBAR + 0x01082588.7.4 Configuration Register 2-MBAR + 0x010C2608.8 Address Bus Mapping2638.8.1 Example-Physical Address Multiplexing264Chapter 9 LocalPlus Bus (External Bus Interface)2669.1 Overview2669.2 Features2669.3 Interface2679.3.1 External Signals2679.3.2 Block Diagram2689.4 Modes of Operation2699.4.1 Non-MUXed Mode2699.4.2 MUXed Mode2729.4.2.1 Address Tenure2739.4.2.2 Data Tenure2739.5 Configuration2749.5.1 Boot Configuration2749.5.2 Chip Selects Configuration2759.5.3 Reset Configuration2759.6 DMA (BestComm) Interface (SCLPC)2769.7 Programmer’s Model2769.7.1 Chip Select / LPC Registers-MBAR + 0x03002769.7.1.1 Chip Select 0/Boot Configuration Register-MBAR + 0x03002789.7.1.2 Chip Select 1 Configuration Register-MBAR + 0x03042809.7.1.3 Chip Select Control Register-MBAR + 0x03182829.7.1.4 Chip Select Status Register-MBAR + 0x031C2839.7.1.5 Chip Select Burst Control Register-MBAR + 0x03282839.7.1.6 Chip Select Deadcycle Control Register-MBAR + 0x032C2869.7.2 SCLPC Registers-MBAR + 0x3C002889.7.2.1 SCLPC Packet Size Register-MBAR + 0x3C002889.7.2.2 SCLPC Start Address Register-MBAR + 0x3C042899.7.2.3 SCLPC Control Register-MBAR + 0x3C082899.7.2.4 SCLPC Enable Register-MBAR + 0x3C0C2909.7.2.5 SCLPC Bytes Done Status Register-MBAR + 0x3C142919.7.3 SCLPC FIFO Registers-MBAR + 0x3C402939.7.3.1 LPC Rx / Tx FIFO Data Word Register-MBAR + 0x3C402939.7.3.2 LPC Rx / Tx FIFO Status Register-MBAR + 0x3C442949.7.3.3 LPC Rx / Tx FIFO Control Register-MBAR + 0x3C482959.7.3.4 LPC Rx / Tx FIFO Alarm Register-MBAR + 0x3C4C2959.7.3.5 LPC Rx / Tx FIFO Read Pointer Register-MBAR + 0x3C502969.7.3.6 LPC Rx / Tx FIFO Write Pointer Register-MBAR + 0x3C54296Chapter 10 PCI Controller29810.1 Overview29810.1.1 Features29810.1.2 Block Diagram29910.2 PCI External Signals29910.2.1 PCI_AD[31:0] - Address/Data Bus30010.2.2 PCI_CBE[3:0] - Command/Byte Enables30010.2.3 PCI_DEVSEL - Device Select30010.2.4 PCI_FRAME - Frame30010.2.5 PCI_IDSEL - Initialization Device Select30010.2.6 PCI_IRDY - Initiator Ready30010.2.6.1 PCI_PAR - Parity30010.2.7 PCI_CLK - PCI Clock30010.2.8 PCI_PERR - Parity Error30010.2.9 PCI_RST - Reset30010.2.10 PCI_SERR - System Error30010.2.11 PCI_STOP - Stop30010.2.12 PCI_TRDY - Target Ready30010.3 Registers30110.3.1 PCI Controller Type 0 Configuration Space30310.3.1.1 Device ID/ Vendor ID Registers PCIIDR(R) -MBAR + 0x0D0030410.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) -MBAR + 0x0D0430510.3.1.3 Revision ID/ Class Code Registers PCICCRIR(R) -MBAR + 0x0D0830710.3.1.4 Configuration 1 Register PCICR1(R/RW) -MBAR + 0x0D0C30710.3.1.5 Base Address Register 0 PCIBAR0(RW) -MBAR + 0x0D1030810.3.1.6 Base Address Register 1 PCIBAR1(RW) -MBAR + 0x0D1430910.3.1.7 CardBus CIS Pointer Register PCICCPR(RW) -MBAR + 0x0D2830910.3.1.8 Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)-MBAR + 0x0D2C30910.3.1.9 Expansion ROM Base Address PCIERBAR(R) -MBAR + 0x0D3030910.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)-MBAR + 0x0D3431010.3.1.11 Configuration 2 Register PCICR2 (R/RW) -MBAR + 0x0D3C31010.3.2 General Control/Status Registers31010.3.2.1 Global Status/Control Register PCIGSCR(RW) -MBAR + 0x0D6031010.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) -MBAR + 0x0D6431310.3.2.3 Target Base Address Translation Register 1 PCITBATR1(RW) -MBAR + 0x0D6831310.3.2.4 Target Control Register PCITCR(RW) -MBAR + 0x0D6C31410.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)-MBAR + 0x0D7031510.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) -MBAR + 0x0D7431610.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) -MBAR + 0x0D7831710.3.2.8 Initiator Window Configuration Register PCIIWCR(RW) -MBAR + 0x0D8031710.3.2.9 Initiator Control Register PCIICR(RW) -MBAR + 0x0D8431810.3.2.10 Initiator Status Register PCIISR(RWC) -MBAR + 0x0D8831910.3.2.11 PCI Arbiter Register PCIARB(RW) -MBAR + 0x0D8C31910.3.2.12 Configuration Address Register PCICAR (RW) -MBAR + 0x0DF832010.3.3 Communication Sub-System Interface Registers32010.3.3.1 Multi-Channel DMA Transmit Interface32010.3.3.1.1 Tx Packet Size PCITPSR(RW) -MBAR + 0x380032110.3.3.1.2 Tx Start Address PCITSAR(RW) -MBAR + 0x380432110.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) -MBAR + 0x380832110.3.3.1.4 Tx Enables PCITER(RW)-MBAR + 0x380C32310.3.3.1.5 Tx Next Address PCITNAR(R) -MBAR + 0x381032410.3.3.1.6 Tx Last Word PCITLWR(R) -MBAR + 0x381432510.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) -MBAR + 0x381832510.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) -MBAR + 0x382032510.3.3.1.9 Tx Status PCITSR(RWC) -MBAR + 0x381C32610.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) -MBAR + 0x384032710.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) -MBAR + 0x384432810.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) -MBAR + 0x384832910.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) -MBAR + 0x384C32910.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) -MBAR + 0x385033110.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW) -MBAR + 0x385433110.3.3.2 Multi-Channel DMA Receive Interface33110.3.3.2.1 Rx Packet Size PCIRPSR(RW) -MBAR + 0x388033210.3.3.2.2 Rx Start Address PCIRSAR (RW) -MBAR + 0x388433210.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) -MBAR + 0x388833210.3.3.2.4 Rx Enables PCIRER (RW) -MBAR + 0x388C33410.3.3.2.5 Rx Next Address PCIRNAR(R) -MBAR + 0x389033510.3.3.2.6 Rx Last Word PCIRLWR(R) -MBAR + 0x389433510.3.3.2.7 Rx Bytes Done Counts PCIRDCR(R) -MBAR + 0x389833610.3.3.2.8 Rx Packets Done Counts PCIRPDCR(R) -MBAR + 0x38A033610.3.3.2.9 Rx Status PCIRSR (R/sw1) -MBAR + 0x389C33710.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) -MBAR + 0x38C033810.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) -MBAR + 0x38C433810.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) -MBAR + 0x38C833910.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) -MBAR + 0x38CC34010.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) -MBAR + 0x38D034110.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR (RW) -MBAR + 0x38D434110.4 Functional Description34110.4.1 PCI Bus Protocol34210.4.1.1 PCI Bus Background34210.4.1.2 Basic Transfer Control34210.4.1.3 PCI Transactions34310.4.1.4 PCI Bus Commands34410.4.1.5 Addressing34510.4.1.5.1 Memory space addressing34510.4.1.5.2 I/O space addressing34610.4.1.5.3 Configuration space addressing and transactions34610.4.1.5.4 Address decoding34710.4.2 Initiator Arbitration34810.4.2.1 Priority Scheme34810.4.3 Configuration Interface34810.4.4 XL bus Initiator Interface34810.4.4.1 Endian Translation34910.4.4.2 Configuration Mechanism35110.4.4.2.1 Type 0 Configuration Translation35110.4.4.2.2 Type 1 Configuration Translation35310.4.4.2.3 Interrupt Acknowledge Transactions35310.4.4.2.4 Special Cycle Transactions35310.4.4.3 Transaction Termination35410.4.5 XL bus Target Interface35410.4.5.1 Reads from Local Memory35510.4.5.2 Local Memory Writes35510.4.5.3 Data Translation35510.4.5.4 Target Abort35610.4.5.5 Latrule Disable35610.4.6 Communication Sub-System Initiator Interface35610.4.6.1 Access Width35710.4.6.2 Addressing35710.4.6.3 Data Translation35710.4.6.4 Initialization35710.4.6.5 Restart and Reset35810.4.6.6 PCI Commands35810.4.6.7 FIFO Considerations35810.4.6.8 Alarms35910.4.6.9 Bus Errors35910.4.7 PCI - Supported Clock Ratios35910.4.8 Interrupts35910.4.8.1 PCI Bus Interrupts35910.4.8.2 Internal Interrupt35910.5 PCI Arbiter35910.6 Application Information36010.6.1 XL bus Initiated Transaction Mapping36010.6.2 Address Maps36110.6.2.1 Address Translation36110.6.2.1.1 Inbound Address Translation36110.6.2.1.2 Outbound Address Translation36210.6.2.1.3 Base Address Register Overview36310.6.3 XL bus Arbitration Priority364Chapter 11 ATA Controller36611.1 Overview36611.2 BestComm Key Features36611.2.1 BestComm Read36611.2.2 BestComm Write36711.3 ATA Register Interface36711.3.1 ATA Host Registers-MBAR + 0x3A0036711.3.1.1 ATA Host Configuration Register-MBAR + 0x3A0036711.3.1.2 ATA Host Status Register-MBAR + 0x3A0436811.3.1.3 ATA PIO Timing 1 Register-MBAR + 0x3A0836811.3.1.4 ATA PIO Timing 2 Register-MBAR + 0x3A0C36911.3.1.5 ATA Multiword DMA Timing 1 Register-MBAR + 0x3A1036911.3.1.6 ATA Multiword DMA Timing 2 Register-MBAR + 0x3A1437011.3.1.7 ATA Ultra DMA Timing 1 Register-MBAR + 0x3A1837011.3.1.8 ATA Ultra DMA Timing 2 Register-MBAR + 0x3A1C37111.3.1.9 ATA Ultra DMA Timing 3 Register-MBAR + 0x 3A2037111.3.1.10 ATA Ultra DMA Timing 4 Register-MBAR + 0x3A2437211.3.1.11 ATA Ultra DMA Timing 5 Register-MBAR + 0x3A2837311.3.1.12 ATA Share Count Register-MBAR + 0x3A2C37311.3.2 ATA FIFO Registers-MBAR + 0x3A0037311.3.2.1 ATA Rx / Tx FIFO Data Word Register-MBAR + 0x3A3C37411.3.2.2 ATA Rx / Tx FIFO Status Register-MBAR + 0x3A4037411.3.2.3 ATA Rx / Tx FIFO Control Register-MBAR + 0x3A4437511.3.2.4 ATA Rx / Tx FIFO Alarm Register-MBAR + 0x3A4837511.3.2.5 ATA Rx / Tx FIFO Read Pointer Register-MBAR + 0x3A4C37611.3.2.6 ATA Rx / Tx FIFO Write Pointer Register-MBAR + 0x3A5037611.3.3 ATA Drive Registers-MBAR + 0x3A0037711.3.3.1 ATA Drive Device Control Register-MBAR + 0x3A5C37711.3.3.2 ATA Drive Alternate Status Register-MBAR + 0x3A5C37811.3.3.3 ATA Drive Data Register-MBAR + 0x3A6037811.3.3.4 ATA Drive Features Register-MBAR + 0x3A6437911.3.3.5 ATA Drive Error Register-MBAR + 0x3A6437911.3.3.6 ATA Drive Sector Count Register-MBAR + 0x3A6838011.3.3.7 ATA Drive Sector Number Register-MBAR + 0x3A6C38011.3.3.8 ATA Drive Cylinder Low Register-MBAR + 0x3A7038111.3.3.9 ATA Drive Cylinder High Register-MBAR + 0x3A7438111.3.3.10 ATA Drive Device / Head Register-MBAR + 0x3A7838211.3.3.11 ATA Drive Device Command Register-MBAR + 0x3A7C38211.3.3.12 ATA Drive Device Status Register-MBAR + 0x3A7C38411.4 ATA Host Controller Operation38511.4.1 PIO State Machine38611.4.2 DMA State Machine38711.4.2.1 Software Requirements38711.5 Signals and Connections38811.6 ATA Interface Description38911.7 ATA Bus Background39111.7.1 Terminology39111.7.2 ATA Modes39211.7.3 ATA Addressing39211.7.3.1 ATA Register Addressing39311.7.3.2 Drive Interrupt39311.7.3.3 Sector Addressing39311.7.3.4 Physical / Logical Addressing Modes39411.7.4 ATA Transactions39511.7.4.1 PIO Mode Transactions39511.7.4.1.1 Class 1-PIO Read39511.7.4.1.2 Class 2-PIO Write39611.7.4.1.3 Class 3-Non-Data Command39711.7.4.2 DMA Protocol39711.7.4.3 Multiword DMA Transactions40011.7.4.3.1 Class 4-DMA Command40011.7.4.4 Ultra DMA Protocol40011.8 ATA RESET / Power-Up40111.8.1 Hardware Reset40111.8.2 Software Reset40111.9 ATA I/O Cable Specifications402Chapter 12 Universal Serial Bus ( USB )40412.1 Overview40412.2 Data Transfer Types40412.3 Host Controller Interface40512.3.1 Communication Channels40512.3.2 Data Structures40612.4 Host Control ( HC ) Operational Registers40812.4.1 Programming Note40812.4.2 Control and Status Partition-MBAR + 0x100040912.4.2.1 USB HC Revision Register-MBAR + 0x100040912.4.2.2 USB HC Control Register-MBAR + 0x100440912.4.2.3 USB HC Command Status Register-MBAR + 0x100841112.4.2.4 USB HC Interrupt Status Register -MBAR + 0x 100C41212.4.2.5 USB HC Interrupt Enable Register-MBAR + 0x 101041312.4.2.6 USB HC Interrupt Disable Register-MBAR + 0x 101441412.4.3 Memory Pointer Partition-MBAR + 0x101841512.4.3.1 USB HC HCCA Register-MBAR + 0x101841612.4.3.2 USB HC Period Current Endpoint Descriptor Register -MBAR + 0x101C41612.4.3.3 USB HC Control Head Endpoint Descriptor Register -MBAR + 0x102041712.4.3.4 USB HC Control Current Endpoint Descriptor Register -MBAR + 0x102441712.4.3.5 USB HC Bulk Head Endpoint Descriptor Register-MBAR + 0x102841712.4.3.6 USB HC Bulk Current Endpoint Descriptor Register-MBAR + 0x102C41812.4.3.7 USB HC Done Head Register-MBAR + 0x103041812.4.4 Frame Counter Partition-MBAR + 0x103441912.4.4.1 USB HC Frame Interval Register-MBAR + 0x103441912.4.4.2 USB HC Frame Remaining Register-MBAR + 0x103842012.4.4.3 USB HC Frame Number Register-MBAR + 0x103C42012.4.4.4 USB HC Periodic Start Register-MBAR + 0x104042112.4.4.5 USB HC LS Threshold Register-MBAR + 0x104442112.4.5 Root Hub Partition-MBAR + 0x104842212.4.5.1 USB HC Rh Descriptor A Register-MBAR + 0x104842212.4.5.2 USB HC Rh Descriptor B Register-MBAR + 0x104C42312.4.5.3 USB HC Rh Status Register-MBAR + 0x105042412.4.5.4 USB HC Rh Port1 Status Register-MBAR + 0x105442512.4.5.5 USB HC Rh Port2 Status Register-MBAR + 0x1058429Chapter 13 BestComm43413.1 Overview43413.2 BestComm Functional Description43413.3 Features summary43513.4 Descriptors43513.5 Tasks43513.6 Memory Map/ Register Definitions43513.7 Task Table (Entry Table)43613.8 Task Descriptor Table43613.9 Variable Table43613.10 Function Descriptor Table43613.11 Context Save Area43613.12 External DMA Request43613.13 External DMA Breakpoint43613.14 BestComm XLB Address Snooping43713.15 BestComm DMA Registers-MBAR + 0x120043713.15.1 SDMA Task Bar Register-MBAR + 0x120043713.15.2 SDMA Current Pointer Register-MBAR + 0x120443813.15.3 SDMA End Pointer Register-MBAR + 0x120843813.15.4 SDMA Variable Pointer Register-MBAR + 0x120C43813.15.5 SDMA Interrupt Vector, PTD Control Register-MBAR + 0x121043913.15.6 SDMA Interrupt Pending Register-MBAR + 0x121444013.15.7 SDMA Interrupt Mask Register-MBAR + 0x121844113.15.8 SDMA Task Control 0 Register-MBAR + 0x121C44213.15.9 SDMA Task Control 2 Register-MBAR + 0x122044313.15.10 SDMA Task Control 4 Register-MBAR + 0x122444413.15.11 SDMA Task Control 6 Register-MBAR + 0x122844413.15.12 SDMA Task Control 8 Register-MBAR + 0x122C44513.15.13 SDMA Task Control A Register-MBAR + 0x123044513.15.14 SDMA Task Control C Register-MBAR + 0x123444613.15.15 SDMA Task Control E Register-MBAR + 0x123844613.15.16 SDMA Initiator Priority 0 Register-MBAR + 0x123C44713.15.17 SDMA Initiator Priority 4 Register-MBAR + 0x124044813.15.18 SDMA Initiator Priority 8 Register-MBAR + 0x124444813.15.19 SDMA Initiator Priority 12 Register-MBAR + 0x124844913.15.20 SDMA Initiator Priority 16 Register-MBAR + 0x124C45013.15.21 SDMA Initiator Priority 20 Register-MBAR + 0x125045113.15.22 SDMA Initiator Priority 24 Register-MBAR + 0x125445113.15.23 SDMA Initiator Priority 28 Register-MBAR + 0x125845213.15.24 SDMA Requestor MuxControl-MBAR + 0x125C45313.15.25 SDMA task Size0-MBAR + 0x126045513.15.26 SDMA task 0 & task Size 1 map45613.15.27 SDMA Reserved Register 1-MBAR + 0x126845613.15.28 SDMA Reserved Register 2-MBAR + 0x126C45713.15.29 SDMA Debug Module Comparator 1, Value 1 Register-MBAR + 0x127045713.15.30 SDMA Debug Module Comparator 2, Value 2 Register-MBAR + 0x127445713.15.31 SDMA Debug Module Control Register-MBAR + 0x127845813.15.32 SDMA Debug Module Status Register-MBAR + 0x127C46013.16 On-Chip SRAM46113.17 Programming Model46113.17.1 Task Table46113.17.1.1 Integer Mode46313.17.1.2 Pack46313.17.2 Variable Table463Chapter 14 Fast Ethernet Controller ( FEC )46614.1 Overview46614.1.1 Features46714.2 Modes of Operation46814.2.1 Full- and Half-Duplex Operation46814.2.2 10 Mbps and 100 Mbps MII Interface Operation46814.2.3 10 Mbps 7-Wire Interface Operation46814.2.4 Address Recognition Options46814.2.5 Internal Loopback46814.3 I / O Signal Overview46814.3.1 Detailed Signal Descriptions46914.3.1.1 MII Ethernet MAC-PHY Interface46914.3.1.2 MII Management Frame Structure47014.3.1.2.1 MII Management Register Set47114.4 FEC Memory Map and Registers47114.4.1 Control and Status (CSR) Memory Map47214.4.2 MIB Block Counters Memory Map47314.5 FEC Registers-MBAR + 0x300047514.5.1 FEC ID Register-MBAR + 0x300047614.5.2 FEC Interrupt Event Register-MBAR + 0x300447714.5.3 FEC Interrupt Enable Register-MBAR + 0x300847914.5.4 FEC Rx Descriptor Active Register-MBAR + 0x301047914.5.5 FEC Tx Descriptor Active Register-MBAR + 0x301448014.5.6 FEC Ethernet Control Register-MBAR + 0x302448114.5.7 FEC MII Management Frame Register-MBAR + 0x304048214.5.8 FEC MII Speed Control Register-MBAR + 0x304448314.5.9 FEC MIB Control Register-MBAR + 0x306448414.5.10 FEC Receive Control Register-MBAR + 0x308448514.5.11 FEC Hash Register-MBAR + 0x308848614.5.12 FEC Tx Control Register-MBAR + 0x30C448614.5.13 FEC Physical Address Low Register-MBAR + 0x30E448714.5.14 FEC Physical Address High Register-MBAR + 0x30E848814.5.15 FEC Opcode / Pause Duration Register-MBAR + 0x30EC48814.5.16 FEC Descriptor Individual Address 1 Registe-MBAR + 0x311848914.5.17 FEC Descriptor Individual Address 2 Register-MBAR + 0x311C48914.5.18 FEC Descriptor Group Address 1 Register-MBAR + 0x312049014.5.19 FEC Descriptor Group Address 2 Register-MBAR + 0x312449014.5.20 FEC Tx FIFO Watermark Register-MBAR + 0x314449114.6 FIFO Interface49214.6.1 FEC Rx FIFO Data Register-MBAR + 0x318449314.7 FEC Tx FIFO Data Register-MBAR + 0x31A449314.7.1 FEC Rx FIFO Status Register-MBAR + 0x318849314.8 FEC Tx FIFO Status Register-MBAR + 0x31A849314.8.1 FEC Rx FIFO Control Register-MBAR + 0x318C49414.8.2 FEC Rx FIFO Last Read Frame Pointer Register-MBAR + 0x319049514.8.3 FEC Rx FIFO Last Write Frame Pointer Register-MBAR + 0x319449614.8.4 FEC Rx FIFO Alarm Pointer Register-MBAR + 0x319849614.8.5 FEC Rx FIFO Read Pointer Register-MBAR + 0x319C49714.8.6 FEC Rx FIFO Write Pointer Register-MBAR + 0x31A049814.8.7 FEC Reset Control Register-MBAR + 0x31C449814.8.8 FEC Transmit FSM Register-MBAR + 0x31C849914.9 Initialization Sequence49914.9.1 Hardware Controlled Initialization49914.9.2 User Initialization (Prior to Asserting ETHER_EN)50014.9.2.1 Microcontroller Initialization50014.9.3 Frame Control/Status Words50014.9.3.1 Receive Frame Status Word50014.9.3.2 Transmit Frame Control Word50114.9.4 Network Interface Options50214.9.5 FEC Frame Reception50214.9.6 Ethernet Address Recognition50314.9.7 Full-Duplex Flow Control50714.9.8 Inter-Packet Gap Time50814.9.9 Collision Handling50814.9.10 Internal and External Loopback50914.9.11 Ethernet Error-Handling Procedure50914.9.11.1 Transmission Errors50914.9.11.2 Reception Errors509Chapter 15 Programmable Serial Controller ( PSC)51215.1 Overview51215.1.1 PSC Functions Overview51315.1.2 Features51415.2 PSC Registers-MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0051515.2.1 Mode Register 1 (0x00)-MR151615.2.2 Mode Register 2 (0x00) - MR251815.2.3 Status Register (0x04) - SR51915.2.4 Clock Select Register (0x04) - CSR52315.2.5 Command Register (0x08)-CR52315.2.6 Rx Buffer Register (0x0C) - RB52615.2.7 Tx Buffer Register (0x0C)-TB52715.2.8 Input Port Change Register (0x10) - IPCR52815.2.9 Auxiliary Control Register (0x10) - ACR52915.2.10 Interrupt Status Register (0x14) - ISR53015.2.11 Interrupt Mask Register (0x14)-IMR53115.2.12 Counter Timer Upper Register (0x18)-CTUR53315.2.13 Counter Timer Lower Register (0x1C)-CTLR53415.2.14 Codec Clock Register (0x20)-CCR53415.2.15 AC97 Slots Register (0x24)-AC97Slots53715.2.16 AC97 Command Register (0x28)-AC97CMD53715.2.17 AC97 Status Data Register (0x2C)-AC97Data53815.2.18 Interrupt Vector Register (0x30)-IVR53815.2.19 Input Port Register (0x34)-IP53915.2.20 Output Port 1 Bit Set (0x38)-OP154015.2.21 Output Port 0 Bit Set (0x3C)-OP054015.2.22 Serial Interface Control Register (0x40)-SICR54115.2.23 Infrared Control 1 (0x44)-IRCR154415.2.24 Infrared Control 2 (0x48)-IRCR254415.2.25 Infrared SIR Divide Register (0x4C)-IRSDR54515.2.26 Infrared MIR Divide Register (0x50)-IRMDR54615.2.27 Infrared FIR Divide Register (0x54)-IRFDR54715.2.28 Rx FIFO Number of Data (0x58)-RFNUM54915.2.29 Tx FIFO Number of Data (0x5C)-TFNUM54915.2.30 Rx FIFO Data (0x60)-RFDATA54915.2.31 Rx FIFO Status (0x64)-RFSTAT54915.2.32 Rx FIFO Control (0x68)-RFCNTL55015.2.33 Rx FIFO Alarm (0x6E)-RFALARM55015.2.34 Rx FIFO Read Pointer (0x72)-RFRPTR55115.2.35 Rx FIFO Write Pointer(0x76)-RFWPTR55115.2.36 Rx FIFO Last Read Frame (0x7A)-RFLRFPTR55115.2.37 Rx FIFO Last Write Frame PTR (0x7C)-RFLWFPTR55215.2.38 Tx FIFO Data (0x80)-TFDATA55215.2.39 Tx FIFO Status (0x84)-TFSTAT55215.2.40 Tx FIFO Control (0x88)-TFCNTL55315.2.41 Tx FIFO Alarm (0x8E)-TFALARM55315.2.42 Tx FIFO Read Pointer (0x92)-TFRPTR55315.2.43 Tx FIFO Write Pointer (0x96)-TFWPTR55415.2.44 Tx FIFO Last Read Frame (0x9A)-TFLRFPTR55415.2.45 Tx FIFO Last Write Frame PTR (0x9C)-TFLWFPTR55415.3 PSC Operation Modes55515.3.1 PSC in UART Mode55515.3.1.1 Block Diagram and Signal Definition for UART Mode55515.3.1.2 UART Clock Generation55715.3.1.3 Transmitting in UART Mode55715.3.1.4 Receiving in UART Mode55815.3.1.5 Configuration Sequence for UART Mode55915.3.2 PSC in Codec Mode56015.3.2.1 Block Diagram and Signal Definition for Codec Mode56115.3.2.2 Codec Clock and FrameSync Generation56215.3.2.3 Transmitting and Receiving in “Soft Modem” Codec Mode56315.3.2.4 Transmitting and Receiving in ESAI Mode (Enhanced Serial Audio Interface)56515.3.2.5 Transmitting and Receiving in “Cell Phone” Mode56715.3.2.6 Transmitting and Receiving in I2S Master Mode56815.3.2.7 Transmitting and Receiving in SPI Mode57015.3.3 PSC in AC97 Mode57215.3.3.1 Block Diagram and Signal Definition for AC97 Mode57315.3.3.2 Generate a reset pulse for the external AC97 Codec device57415.3.3.3 AC97 Low-Power Mode57415.3.3.4 Transmitting and Receiving in “Normal” AC97 Mode57515.3.3.5 Transmitting and Receiving in “Enhanced” AC97 Mode57515.3.4 PSC in IrDA mode57615.3.4.1 PSC in SIR Mode57615.3.4.1.1 Block Diagram and Signal Definition for SIR Mode57615.3.4.1.2 Transmitting and Receiving in SIR Mode57715.3.4.1.3 Configuration Sequence Example for SIR Mode57815.3.4.2 PSC in MIR Mode57815.3.4.2.1 Block Diagram and Signal Definition for MIR Mode57815.3.4.2.2 Transmitting and Receiving in MIR Mode57915.3.4.2.3 Serial Interaction Pulse (SIP)58015.3.4.2.4 Configuration Sequence Example for MIR Mode58015.3.4.3 PSC in FIR Mode58115.3.4.3.1 Block Diagram and Signal Definition for FIR Mode58115.3.4.3.2 Transmitting and Receiving in FIR Mode58115.3.4.3.3 Configuration Sequence Example for FIR Mode58215.4 PSC FIFO System58215.4.1 RX FIFO58415.4.2 TX FIFO58515.4.3 Looping Modes58515.4.3.1 Automatic Echo Mode58515.4.3.2 Local Loop-Back Mode58515.4.3.3 Remote Loop-Back Mode58615.4.4 Multidrop Mode586Chapter 16 XLB Arbiter58816.1 Overview58816.1.1 Purpose58816.1.1.1 Prioritization58816.1.1.2 Bus Grant Mechanism58916.1.1.2.1 Bus Grant58916.1.1.2.2 Parking Modes58916.1.1.3 Configuration, Status, and Interrupt Generation58916.1.1.4 Watchdog Functions58916.1.1.4.1 Timer Functions58916.1.1.4.2 Other Tenure Ending Conditions59016.2 XLB Arbiter Registers-MBAR + 0x1F0059016.2.1 Arbiter Configuration Register (R/W)-MBAR + 0x1F4059016.2.2 Arbiter Version Register (R)-MBAR + 0x1F4459216.2.3 Arbiter Status Register (R/W)-MBAR + 0x1F4859216.2.4 Arbiter Interrupt Enable Register (R/W)-MBAR + 0x1F4C59316.2.5 Arbiter Address Capture Register (R)-MBAR + 0x1F5059416.2.6 Arbiter Bus Signal Capture Register (R)-MBAR + 0x1F5459516.2.7 Arbiter Address Tenure Time-Out Register (R/W)-MBAR + 0x1F5859516.2.8 Arbiter Data Tenure Time-Out Register (R/W)-MBAR + 0x1F5C59616.2.9 Arbiter Bus Activity Time-Out Register (R/W)-MBAR + 0x1F6059616.2.10 Arbiter Master Priority Enable Register (R/W)-MBAR + 0x1F6459716.2.11 Arbiter Master Priority Register (R/W)-MBAR + 0x1F6859816.2.12 Arbiter Snoop Window Register (RW)-MBAR + 0x1F7059916.2.13 Arbiter Reserved Registers-MBAR + 0x1F00-1F3C, 0x1F74-1FFF600Chapter 17 Serial Peripheral Interface ( SPI )60217.1 Overview60217.1.1 Features60217.1.2 Modes of Operation60317.2 SPI Signal Description60317.2.1 Master In / Slave Out ( MISO )60317.2.2 Master Out / Slave In ( MOSI )60317.2.3 Serial Clock ( SCK )60317.2.4 Slave-Select ( SS )60317.3 SPI Registers-MBAR + 0x0F0060417.3.1 SPI Control Register 1-MBAR + 0x0F0060417.3.2 SPI Control Register 2-MBAR + 0x0F0160517.3.3 SPI Baud Rate Register-MBAR + 0x0F0460617.3.4 SPI Status Register -MBAR + 0x0F0560717.3.5 SPI Data Register-MBAR + 0x0F0960817.3.6 SPI Port Data Register-MBAR + 0x0F0D60817.3.7 SPI Data Direction Register-MBAR + 0x0F1060817.4 Functional Description60917.4.1 General60917.4.2 Master Mode60917.4.3 Slave Mode61017.4.4 Transmission Formats61017.4.4.1 Clock Phase and Polarity Controls61117.4.4.2 CPHA = 0 Transfer Format61117.4.4.3 CPHA = 1 Transfer Format61217.4.5 SPI Baud Rate Generation61317.4.6 Special Features61417.4.6.1 SS Output61417.4.6.2 Bidirectional Mode (MOMI or SISO)61417.4.7 Error Conditions61517.4.7.1 Write Collision Error61517.4.7.2 Mode Fault Error61517.4.8 Low Power Mode Options61517.4.8.1 SPI in Run Mode61517.4.8.2 SPI in Wait Mode61517.4.8.3 SPI in Stop Mode61617.4.9 SPI Interrupts61617.4.9.1 MODF Description61617.4.9.2 SPIF Description616Chapter 18 Inter-Integrated Circuit ( I 2 C )61818.1 Overview61818.1.1 Features61818.2 I2C Controller61918.2.1 START Signal61918.2.2 STOP Signal61918.2.2.1 Slave Address Transmission62018.2.2.2 Data Transfer62018.2.2.3 Acknowledge62018.2.2.4 Repeated Start62118.2.2.5 Clock Synchronization and Arbitration62118.3 I2C Interface Registers62218.3.1 I2C Address Register (MADR)-MBAR + 0x3D00 / 0x3D4062318.3.2 I2C Frequency Divider Register (MFDR)-MBAR + 0x3D04 / 0x3D4462318.3.3 I2C Control Register (MCR)-MBAR + 0x3D08 / 0x3D4863018.3.4 I2C Status Register (MSR)-MBAR + 0x3D0C / 0x3D4C63218.3.5 I2C Data I / O Register (MDR)-MBAR+ x3D10 / 0x3D5063318.3.6 I2C Interrupt Control Register-MBAR + 0x3D2063418.3.7 I2C Filter Register (MIFR)-MBAR + 0x3D2463518.4 Initialization Sequence63618.5 Transfer Initiation and Interrupt63618.5.1 Post-Transfer Software Response63618.5.2 Slave Mode63618.5.3 Special Note on AKF637Chapter 19 Controller Area Network ( MSCAN )64019.1 Overview64019.2 Features64119.3 External Signals64119.3.1 RXCAN - CAN Receiver Input Pin64119.3.2 TXCAN - CAN Transmitter Output Pin64119.4 CAN System64119.5 Memory Map / Register Definition64219.5.1 Module Memory Map64219.5.2 Register Descriptions64419.5.3 MSCAN Control Register 0 (CANCTL0)-MBAR + 0x0900 / 0x98064419.5.4 MSCAN Control Register 1 (CANCTL1)-MBAR + 0x0901 / 0x98164619.5.5 MSCAN Bus Timing Register 0 (CANBTR0)-MBAR + 0x0904 / 0x98464719.5.6 MSCAN Bus Timing Register 1 (CANBTR1)-MBAR + 0x0905 / 0x98564819.5.7 MSCAN Receiver Flag Register (CANRFLG)-MBAR+0x0908 / 0x98864919.5.8 MSCAN Receiver Interrupt Enable Register (CANRIER)-MBAR + 0x0909 / 0x98965119.5.9 MSCAN Transmitter Flag Register (CANTFLG)-MBAR + 0x090C / 0x98C65219.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)-MBAR+0x090D / 0x098D65319.5.11 MSCAN Transmitter Message Abort Request (CANTARQ)-MBAR + 0x0910 / 0x099065319.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)-MBAR +0x0911 / 0x099165419.5.13 MSCAN Transmit Buffer Selection (CANTBSEL)-MBAR + 0x0914 /0x099165419.5.14 MSCAN ID Acceptance Control Register (CANIDAC)-MBAR + 0x0915 / 0x099565519.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C65619.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D65619.5.17 MSCAN ID Acceptance Registers (CANIDAR0-7)-MBAR + 0x0920 / 0x09A065719.5.18 MSCAN ID Mask Register (CANIDMR0-7)-MBAR + 0x0928 / 0x09A865919.6 Programmer’s Model of Message Storage66119.6.1 Identifier Registers (IDR0-3)66319.6.2 Data Segment Registers (DSR0-7)66319.6.3 Data Length Register (DLR)66419.6.4 MSCAN Transmit Buffer Priority Register (TBPR)-MBAR + 0x0979 / 0x09F966419.6.5 MSCAN Time Stamp Register High (TSRH)-MBAR + 0x097C / 0x09FC66519.6.6 MSCAN Time Stamp Register Low (TSRL)-MBAR + 0x097D / 0x09FD66519.7 Functional Description66519.7.1 General66519.7.2 Message Storage66619.7.2.1 Message Transmit Background66619.7.2.2 Transmit Structures66719.7.2.3 Receive Structures66719.7.3 Identifier Acceptance Filter66819.7.4 Protocol Violation Protection67019.7.5 Clock System67119.7.6 Timer Link67319.7.7 Modes of Operation67319.7.7.1 Normal Modes67319.7.7.2 Listen-Only Mode67319.7.8 Low Power Options67319.7.8.1 CPU Run Mode67419.7.8.2 CPU Sleep Mode67419.7.8.3 CPU Deep Sleep Mode67419.7.8.4 MSCAN Sleep Mode67419.7.8.5 MSCAN Initialization Mode67519.7.8.6 MSCAN Power Down Mode67619.7.8.7 Programmable Wake-Up Function67619.7.9 Description of Interrupt Operation67619.7.9.1 Transmit Interrupt67719.7.9.2 Receive Interrupt67719.7.9.3 Wake-Up Interrupt67719.7.9.4 Error Interrupt67819.7.10 Interrupt Acknowledge67819.7.11 Recovery from STOP or WAIT678Chapter 20 Byte Data Link Controller (BDLC)68020.1 Overview68020.2 Features68020.3 Modes of Operation68020.4 Block Diagram68320.5 Signal Description68420.6 Overview68420.6.1 Detailed Signal Descriptions68420.6.1.1 TXB - BDLC Transmit Pin68420.6.1.2 RXB - BDLC Receive Pin68420.7 Memory Map and Registers68420.7.1 Overview68420.7.2 Module Memory Map68420.7.3 Register Descriptions68420.7.3.1 BDLC Control Register 1 (DLCBCR1)-MBAR + 0x130068420.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x130068620.7.3.3 BDLC Control Register 2 (DLCBCR2) - MBAR + 0x130468720.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x130569120.7.3.5 BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0x130869120.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x130969320.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C69420.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D69420.8 Functional Description69520.8.1 General69520.8.1.1 J1850 Frame Format69520.8.1.2 J1850 VPW Symbols69620.8.1.3 J1850 VPW Valid/Invalid Bits & Symbols69820.8.1.4 J1850 Bus Errors70520.8.2 Mux Interface70620.8.2.1 Mux Interface - Rx Digital Filter70620.8.3 Protocol Handler70720.8.3.1 Protocol Architecture70820.8.4 Transmitting A Message70920.8.4.1 BDLC Transmission Control Bits70920.8.4.2 Transmitting Exceptions71020.8.4.3 Aborting a Transmission71120.8.5 Receiving A Message71220.8.5.1 BDLC Reception Control Bits71320.8.5.2 Receiving a Message with the BDLC module71320.8.5.3 Filtering Received Messages71320.8.5.4 Receiving Exceptions71320.8.6 Transmitting An In-Frame Response (IFR)71520.8.6.1 IFR Types Supported by the BDLC module71620.8.6.2 BDLC IFR Transmit Control Bits71620.8.6.3 Transmit Single Byte IFR71720.8.6.4 Transmit Multi-Byte IFR 171720.8.6.5 Transmit Multi-Byte IFR 071720.8.6.6 Transmitting An IFR with the BDLC module71720.8.6.7 Transmitting IFR Exceptions72120.8.7 Receiving An In-Frame Response (IFR)72220.8.7.1 Receiving an IFR with the BDLC module72320.8.7.2 Receiving IFR Exceptions72420.8.8 Special BDLC Module Operations72420.8.8.1 Transmitting Or Receiving A Block Mode Message72420.8.8.2 Transmitting Or Receiving A Message In 4X Mode72520.8.9 BDLC Module Initialization72620.8.9.1 Initialization Sequence72620.8.9.2 Initializing the Configuration Bits72720.8.9.3 Exiting Loopback Mode and Enabling the BDLC module72720.8.9.4 Enabling BDLC Interrupts72720.9 Resets72920.9.1 General729Chapter 21 Debug Support and JTAG Interface73021.1 Overview73021.2 TAP Link Module (TLM) and Slave TAP Implementation73021.3 TLM and TAP Signal Descriptions73321.3.1 Test Reset ( TRST )73321.3.2 Test Clock ( TCK )73321.3.3 Test Mode Select ( TMS )73321.3.4 Test Data In ( TDI )73321.3.5 Test Data Out ( TDO )73421.4 Slave Test Reset ( STRST )73421.4.1 Enable Slave-ENA [ 0 : n ]73421.4.2 Select DR Link-SEL [ 0 : n ]73421.4.3 Slave Test Data Out-STDO [ 0 : n ]73421.5 TAP State Machines73421.6 e300 Core JTAG / COP Serial Interface73521.7 TLM Link DR Instructions73621.7.1 TLM : TLMENA73721.7.2 TLM : PPCENA73721.8 TLM Test Instructions73721.8.1 IDCODE73721.8.1.1 Device ID Register73721.8.2 BYPASS73721.8.3 SAMPLE / PRELOAD73721.8.4 EXTEST73821.8.5 CLAMP73821.8.6 HIGHZ73821.9 e300 COP / BDM Interface738Appendix A Acronyms and Terms740Appendix B List of Registers752Размер: 4,7 МБСтраницы: 762Язык: EnglishПросмотреть
Справочник ПользователяСодержаниеMPC5200B Users Guide1Chapter 1 Introduction361.1 Overview361.1.1 Features361.2 Architecture371.2.1 Embedded e300 Core401.2.2 BestComm I / O Subsystem411.2.2.1 Programmable Serial Controllers ( PSCs )411.2.2.2 10 / 100 Ethernet Controller411.2.2.3 Universal Serial Bus ( USB )411.2.2.4 Infrared Support411.2.2.5 Inter-Integrated Circuit ( I 2 C )411.2.2.6 Serial Peripheral Interface ( SPI )411.2.3 Controller Area Network ( CAN )411.2.4 Byte Data Link Controller - Digital BDLC-D421.2.5 System Level Interfaces421.2.5.1 Chip Selects421.2.5.2 Interrupt Controller421.2.5.3 Timers421.2.5.4 General Purpose Input / Outputs ( GPIO )421.2.5.5 Functional Pin Multiplexing431.2.5.6 Real-Time Clock ( RTC )431.2.6 SDRAM Controller and Interface431.2.7 Multi-Function External LocalPlus Bus431.2.8 Power Management431.2.9 Systems Debug and Test441.2.10 Physical Characteristics44Chapter 2 Signal Descriptions462.1 Overview462.2 Pinout Tables49Chapter 3 Memory Map1203.1 Overview1203.2 Internal Register Memory Map1213.3 MPC5200B Memory Map1223.3.1 MPC5200B Internal Register Space1223.3.2 External Busses1223.3.2.1 SDRAM Bus1223.3.2.2 LocalPlus Bus1233.3.3 Memory Map Space Register Description1243.3.3.1 Memory Address Base Register -MBAR + 0x00001243.3.3.2 Boot and Chip Select Addresses1243.3.3.3 SDRAM Chip Select Configuration Registers1253.3.3.4 IPBI Control Register and Wait State Enable -MBAR+0x0054127Chapter 4 Resets and Reset Configuration1284.1 Overview1284.2 Hard and Soft Reset Pins1284.2.1 Power-On Reset-PORRESET1284.2.2 Hard Reset-HRESET1284.2.3 Soft Reset-SRESET1294.3 Reset Sequence1294.4 Reset Operation1294.5 Other Resets1304.6 Reset Configuration131Chapter 5 Clocks and Power Management1345.1 Overview1345.2 Clock Distribution Module (CDM)1345.3 MPC5200B Clock Domains1345.3.1 MPC5200B Top Level Clock Relations1365.3.2 e300 Core Clock Domain1385.3.3 Processor Bus (XLB ) Clock Domain1405.3.4 SDRAM Memory Controller Clock Domain1405.3.5 IPB Clock Domain1415.3.6 PCI Clock Domain1415.4 Power Management1425.4.1 Full-Power Mode1425.4.2 Power Conservation Modes1425.4.3 e300 Core Power Modes1425.4.3.1 Dynamic Power Mode1435.4.3.2 Doze Mode1435.4.3.3 Nap Mode1435.4.3.4 Sleep Mode1435.4.4 Deep-Sleep Mode1435.4.4.1 Entering Deep Sleep1445.4.4.2 Exiting Deep Sleep1445.5 CDM Registers1445.5.1 CDM JTAG ID Number Register-MBAR + 0x02001455.5.2 CDM Power On Reset Configuration Register-MBAR + 0x02041455.5.3 CDM Bread Crumb Register-MBAR + 0x02081475.5.4 CDM Configuration Register-MBAR + 0x020C1475.5.5 CDM 48MHz Fractional Divider Configuration Register-MBAR + 0x02101485.5.6 CDM Clock Enable Register-MBAR + 0x02141495.5.7 CDM System Oscillator Configuration Register-MBAR + 0x02181505.5.8 CDM Clock Control Sequencer Configuration Register-MBAR + 0x021C1515.5.9 CDM Soft Reset Register-MBAR + 0x02201535.5.10 CDM System PLL Status Register-MBAR + 0x02241535.5.11 PSC1 Mclock Config Register-MBAR + 0x02281545.5.12 PSC2 Mclock Config Register-MBAR + 0x022C1555.5.13 PSC3 Mclock Config Register-MBAR + 0x02301555.5.14 PSC6 (IrDA) Mclock Config Register-MBAR + 0x0234156Chapter 6 e300 Processor Core1586.1 Overview1586.2 MPC5200B e300 Processor Core Functional Overview1586.3 e300 Core Reference Manual1596.4 Not supported e300 Core Features1596.4.1 Not supported instruction1596.4.2 Not supported XLB parity feature159Chapter 7 System Integration Unit ( SIU )1607.1 Overview1607.2 Interrupt Controller1607.2.1 Block Description1607.2.1.1 Machine Check Pin-core_mcp1617.2.1.2 System Management Interrupt-core_smi1617.2.1.3 Standard Interrupt-core_int1617.2.2 Interface Description1637.2.3 Programming Note1637.2.4 Interrupt Controller Registers1647.2.4.1 ICTL Peripheral Interrupt Mask Register-MBAR + 0x05001647.2.4.2 ICTL Peripheral Priority and HI / LO Select 1 Register -MBAR + 0x05041667.2.4.3 ICTL Peripheral Priority and HI / LO Select 2 Register -MBAR + 0x05081677.2.4.4 ICTL Peripheral Priority and HI / LO Select 3 Register -MBAR + 0x050C1677.2.4.5 ICTL External Enable and External Types Register -MBAR + 0x05101687.2.4.6 ICTL Critical Priority and Main Interrupt Mask Register-MBAR + 0x05141697.2.4.7 ICTL Main Interrupt Priority and INT / SMI Select 1 Register -MBAR + 0x05181717.2.4.8 ICTL Main Interrupt Priority and INT / SMI Select 2 Register-MBAR + 0x051C1727.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register-MBAR + 0x05241737.2.4.10 ICTL Critical Interrupt Status All Register-MBAR + 0x05281747.2.4.11 ICTL Main Interrupt Status All Register-MBAR + 0x052C1757.2.4.12 ICTL Peripheral Interrupt Status All Register-MBAR + 0x05301767.2.4.13 ICTL Peripheral Interrupt Status All Register-MBAR + 0x05381777.2.4.14 ICTL Main Interrupt Emulation All Register-MBAR + 0x05401787.2.4.15 ICTL Peripheral Interrupt Emulation All Register-MBAR + 0x05441797.2.4.16 ICTL IRQ Interrupt Emulation All Register-MBAR + 0x05481807.3 General Purpose I / O ( GPIO )1817.3.1 GPIO Pin Multiplexing1847.3.1.1 PSC1 ( UART1 / AC97 / CODEC1 )1857.3.1.2 PSC2 ( CAN1/2/UART2 / AC97 / CODEC2 )1857.3.1.3 PSC3 ( USB2 / CODEC3 / SPI / UART3 )1857.3.1.4 USB1/ RST_CONFIG1857.3.1.5 Ethernet / USB2 /UART4/5/J1850/ RST_CONFIG1857.3.1.6 PSC61867.3.1.7 I2C1867.3.1.8 GPIO Timer Pins1867.3.1.9 Dedicated GPIO Port1877.3.2 GPIO Programmer’s Model1877.3.2.1 GPIO Standard Registers-MBAR + 0x0B001877.3.2.1.1 GPS Port Configuration Register-MBAR + 0x0B001887.3.2.1.2 GPS Simple GPIO Enables Register-MBAR + 0x0B041907.3.2.1.3 GPS Simple GPIO Open Drain Type Register -MBAR + 0x0B081927.3.2.1.4 GPS Simple GPIO Data Direction Register-MBAR + 0x0B0C1937.3.2.1.5 GPS Simple GPIO Data Output Values Register -MBAR + 0x0B101967.3.2.1.6 GPS Simple GPIO Data Input Values Register -MBAR + 0x0B141977.3.2.1.7 GPS GPIO Output-Only Enables Register -MBAR + 0x0B181987.3.2.1.8 GPS GPIO Output-Only Data Value Out Register -MBAR + 0x0B1C1997.3.2.1.9 GPS GPIO Simple Interrupt Enable Register-MBAR + 0x0B202007.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register -MBAR + 0x0B242017.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register -MBAR + 0x0B282027.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register -MBAR + 0x0B2C2027.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register -MBAR + 0x0B302037.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register -MBAR + 0x0B342047.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register -MBAR + 0x0B382047.3.2.1.16 GPS GPIO Simple Interrupt Status Register-MBAR + 0x0B3C2057.3.2.2 WakeUp GPIO Registers-MBAR + 0x0C002067.3.2.2.1 GPW WakeUp GPIO Enables Register-MBAR + 0x0C002067.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register -MBAR + 0x0C042077.3.2.2.3 GPW WakeUp GPIO Data Direction Register-MBAR + 0x0C082077.3.2.2.4 GPW WakeUp GPIO Data Value Out Register -MBAR + 0x0C0C2087.3.2.2.5 GPW WakeUp GPIO Interrupt Enable Register-MBAR + 0x0C102097.3.2.2.6 GPW WakeUp GPIO Individual Interrupt Enable Register -MBAR + 0x0C142097.3.2.2.7 GPW WakeUp GPIO Interrupt Types Register-MBAR + 0x0C182107.3.2.2.8 GPW WakeUp GPIO Master Enables Register -MBAR + 0x0C1C2117.3.2.2.9 GPW WakeUp GPIO Data Input Values Register -MBAR + 0x0C202127.3.2.2.10 GPW WakeUp GPIO Status Register-MBAR + 0x0C242137.4 General Purpose Timers ( GPT )2147.4.1 Timer Configuration Method2147.4.2 Mode Overview2147.4.3 Programming Notes2147.4.4 GPT Registers-MBAR + 0x06002157.4.4.1 GPT 0 Enable and Mode Select Register-MBAR + 0x06002157.4.4.2 GPT 0 Counter Input Register-MBAR + 0x06042187.4.4.3 GPT 0 PWM Configuration Register-MBAR + 0x06082197.4.4.4 GPT 0 Status Register-MBAR + 0x060C2207.5 Slice Timers2217.5.1 SLT Registers-MBAR + 0x07002217.5.1.1 SLT 0 Terminal Count Register-MBAR + 0x07002227.5.1.2 SLT 0 Control Register-MBAR + 0x07042227.5.1.3 SLT 0 Count Value Register-MBAR + 0x07082237.5.1.4 SLT 0 Timer Status Register-MBAR + 0x070C2247.6 Real-Time Clock2247.6.1 Real-Time Clock Signals2257.6.2 Programming Note2257.6.3 RTC Interface Registers-MBAR + 0x08002257.6.3.1 RTC Time Set Register-MBAR + 0x08002267.6.3.2 RTC Date Set Register-MBAR + 0x08042277.6.3.3 RTC New Year and Stopwatch Register-MBAR + 0x08082287.6.3.4 RTC Alarm and Interrupt Enable Register-MBAR + 0x080C2287.6.3.5 RTC Current Time Register-MBAR + 0x08102297.6.3.6 RTC Current Date Register-MBAR + 0x08142307.6.3.7 RTC Alarm and Stopwatch Interrupt Register-MBAR + 0x08182307.6.3.8 RTC Periodic Interrupt and Bus Error Register-MBAR + 0x081C2317.6.3.9 RTC Test Register/Divides Register-MBAR + 0x0820232Chapter 8 SDRAM Memory Controller2348.1 Overview2348.2 Terminology and Notation2348.2.1 “Endian”-ness2348.3 Features2358.3.1 Devices Supported2368.4 Functional Description2488.4.1 External Signals (SDRAM Side)2488.4.2 Block Diagram2498.4.3 Transfer Size2498.4.4 Commands2508.4.4.1 Load Mode/Extended Mode Register Command2508.4.4.2 Precharge All Banks Command2518.4.4.3 Row and Bank Active Command2518.4.4.4 Read Command2518.4.4.5 Write Command2518.4.4.6 Burst Terminate Command2528.4.4.7 Auto Refresh Command2528.4.4.8 Self Refresh and Power Down Commands2528.5 Operation2528.5.1 Power-Up Initialization2528.5.2 Read Clock2538.6 Programming the SDRAM Controller2538.7 Memory Controller Registers (MBAR+0x0100:0x010C)2538.7.1 Mode Register-MBAR + 0x01002538.7.2 Control Register-MBAR + 0x01042558.7.3 Configuration Register 1-MBAR + 0x01082588.7.4 Configuration Register 2-MBAR + 0x010C2608.8 Address Bus Mapping2638.8.1 Example-Physical Address Multiplexing264Chapter 9 LocalPlus Bus (External Bus Interface)2669.1 Overview2669.2 Features2669.3 Interface2679.3.1 External Signals2679.3.2 Block Diagram2689.4 Modes of Operation2699.4.1 Non-MUXed Mode2699.4.2 MUXed Mode2729.4.2.1 Address Tenure2739.4.2.2 Data Tenure2739.5 Configuration2749.5.1 Boot Configuration2749.5.2 Chip Selects Configuration2759.5.3 Reset Configuration2759.6 DMA (BestComm) Interface (SCLPC)2769.7 Programmer’s Model2769.7.1 Chip Select / LPC Registers-MBAR + 0x03002769.7.1.1 Chip Select 0/Boot Configuration Register-MBAR + 0x03002789.7.1.2 Chip Select 1 Configuration Register-MBAR + 0x03042809.7.1.3 Chip Select Control Register-MBAR + 0x03182829.7.1.4 Chip Select Status Register-MBAR + 0x031C2839.7.1.5 Chip Select Burst Control Register-MBAR + 0x03282839.7.1.6 Chip Select Deadcycle Control Register-MBAR + 0x032C2869.7.2 SCLPC Registers-MBAR + 0x3C002889.7.2.1 SCLPC Packet Size Register-MBAR + 0x3C002889.7.2.2 SCLPC Start Address Register-MBAR + 0x3C042899.7.2.3 SCLPC Control Register-MBAR + 0x3C082899.7.2.4 SCLPC Enable Register-MBAR + 0x3C0C2909.7.2.5 SCLPC Bytes Done Status Register-MBAR + 0x3C142919.7.3 SCLPC FIFO Registers-MBAR + 0x3C402939.7.3.1 LPC Rx / Tx FIFO Data Word Register-MBAR + 0x3C402939.7.3.2 LPC Rx / Tx FIFO Status Register-MBAR + 0x3C442949.7.3.3 LPC Rx / Tx FIFO Control Register-MBAR + 0x3C482959.7.3.4 LPC Rx / Tx FIFO Alarm Register-MBAR + 0x3C4C2959.7.3.5 LPC Rx / Tx FIFO Read Pointer Register-MBAR + 0x3C502969.7.3.6 LPC Rx / Tx FIFO Write Pointer Register-MBAR + 0x3C54296Chapter 10 PCI Controller29810.1 Overview29810.1.1 Features29810.1.2 Block Diagram29910.2 PCI External Signals29910.2.1 PCI_AD[31:0] - Address/Data Bus30010.2.2 PCI_CBE[3:0] - Command/Byte Enables30010.2.3 PCI_DEVSEL - Device Select30010.2.4 PCI_FRAME - Frame30010.2.5 PCI_IDSEL - Initialization Device Select30010.2.6 PCI_IRDY - Initiator Ready30010.2.6.1 PCI_PAR - Parity30010.2.7 PCI_CLK - PCI Clock30010.2.8 PCI_PERR - Parity Error30010.2.9 PCI_RST - Reset30010.2.10 PCI_SERR - System Error30010.2.11 PCI_STOP - Stop30010.2.12 PCI_TRDY - Target Ready30010.3 Registers30110.3.1 PCI Controller Type 0 Configuration Space30310.3.1.1 Device ID/ Vendor ID Registers PCIIDR(R) -MBAR + 0x0D0030410.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) -MBAR + 0x0D0430510.3.1.3 Revision ID/ Class Code Registers PCICCRIR(R) -MBAR + 0x0D0830710.3.1.4 Configuration 1 Register PCICR1(R/RW) -MBAR + 0x0D0C30710.3.1.5 Base Address Register 0 PCIBAR0(RW) -MBAR + 0x0D1030810.3.1.6 Base Address Register 1 PCIBAR1(RW) -MBAR + 0x0D1430910.3.1.7 CardBus CIS Pointer Register PCICCPR(RW) -MBAR + 0x0D2830910.3.1.8 Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)-MBAR + 0x0D2C30910.3.1.9 Expansion ROM Base Address PCIERBAR(R) -MBAR + 0x0D3030910.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)-MBAR + 0x0D3431010.3.1.11 Configuration 2 Register PCICR2 (R/RW) -MBAR + 0x0D3C31010.3.2 General Control/Status Registers31010.3.2.1 Global Status/Control Register PCIGSCR(RW) -MBAR + 0x0D6031010.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) -MBAR + 0x0D6431310.3.2.3 Target Base Address Translation Register 1 PCITBATR1(RW) -MBAR + 0x0D6831310.3.2.4 Target Control Register PCITCR(RW) -MBAR + 0x0D6C31410.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)-MBAR + 0x0D7031510.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) -MBAR + 0x0D7431610.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) -MBAR + 0x0D7831710.3.2.8 Initiator Window Configuration Register PCIIWCR(RW) -MBAR + 0x0D8031710.3.2.9 Initiator Control Register PCIICR(RW) -MBAR + 0x0D8431810.3.2.10 Initiator Status Register PCIISR(RWC) -MBAR + 0x0D8831910.3.2.11 PCI Arbiter Register PCIARB(RW) -MBAR + 0x0D8C31910.3.2.12 Configuration Address Register PCICAR (RW) -MBAR + 0x0DF832010.3.3 Communication Sub-System Interface Registers32010.3.3.1 Multi-Channel DMA Transmit Interface32010.3.3.1.1 Tx Packet Size PCITPSR(RW) -MBAR + 0x380032110.3.3.1.2 Tx Start Address PCITSAR(RW) -MBAR + 0x380432110.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) -MBAR + 0x380832110.3.3.1.4 Tx Enables PCITER(RW)-MBAR + 0x380C32310.3.3.1.5 Tx Next Address PCITNAR(R) -MBAR + 0x381032410.3.3.1.6 Tx Last Word PCITLWR(R) -MBAR + 0x381432510.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) -MBAR + 0x381832510.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) -MBAR + 0x382032510.3.3.1.9 Tx Status PCITSR(RWC) -MBAR + 0x381C32610.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) -MBAR + 0x384032710.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) -MBAR + 0x384432810.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) -MBAR + 0x384832910.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) -MBAR + 0x384C32910.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) -MBAR + 0x385033110.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW) -MBAR + 0x385433110.3.3.2 Multi-Channel DMA Receive Interface33110.3.3.2.1 Rx Packet Size PCIRPSR(RW) -MBAR + 0x388033210.3.3.2.2 Rx Start Address PCIRSAR (RW) -MBAR + 0x388433210.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) -MBAR + 0x388833210.3.3.2.4 Rx Enables PCIRER (RW) -MBAR + 0x388C33410.3.3.2.5 Rx Next Address PCIRNAR(R) -MBAR + 0x389033510.3.3.2.6 Rx Last Word PCIRLWR(R) -MBAR + 0x389433510.3.3.2.7 Rx Bytes Done Counts PCIRDCR(R) -MBAR + 0x389833610.3.3.2.8 Rx Packets Done Counts PCIRPDCR(R) -MBAR + 0x38A033610.3.3.2.9 Rx Status PCIRSR (R/sw1) -MBAR + 0x389C33710.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) -MBAR + 0x38C033810.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) -MBAR + 0x38C433810.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) -MBAR + 0x38C833910.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) -MBAR + 0x38CC34010.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) -MBAR + 0x38D034110.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR (RW) -MBAR + 0x38D434110.4 Functional Description34110.4.1 PCI Bus Protocol34210.4.1.1 PCI Bus Background34210.4.1.2 Basic Transfer Control34210.4.1.3 PCI Transactions34310.4.1.4 PCI Bus Commands34410.4.1.5 Addressing34510.4.1.5.1 Memory space addressing34510.4.1.5.2 I/O space addressing34610.4.1.5.3 Configuration space addressing and transactions34610.4.1.5.4 Address decoding34710.4.2 Initiator Arbitration34810.4.2.1 Priority Scheme34810.4.3 Configuration Interface34810.4.4 XL bus Initiator Interface34810.4.4.1 Endian Translation34910.4.4.2 Configuration Mechanism35110.4.4.2.1 Type 0 Configuration Translation35110.4.4.2.2 Type 1 Configuration Translation35310.4.4.2.3 Interrupt Acknowledge Transactions35310.4.4.2.4 Special Cycle Transactions35310.4.4.3 Transaction Termination35410.4.5 XL bus Target Interface35410.4.5.1 Reads from Local Memory35510.4.5.2 Local Memory Writes35510.4.5.3 Data Translation35510.4.5.4 Target Abort35610.4.5.5 Latrule Disable35610.4.6 Communication Sub-System Initiator Interface35610.4.6.1 Access Width35710.4.6.2 Addressing35710.4.6.3 Data Translation35710.4.6.4 Initialization35710.4.6.5 Restart and Reset35810.4.6.6 PCI Commands35810.4.6.7 FIFO Considerations35810.4.6.8 Alarms35910.4.6.9 Bus Errors35910.4.7 PCI - Supported Clock Ratios35910.4.8 Interrupts35910.4.8.1 PCI Bus Interrupts35910.4.8.2 Internal Interrupt35910.5 PCI Arbiter35910.6 Application Information36010.6.1 XL bus Initiated Transaction Mapping36010.6.2 Address Maps36110.6.2.1 Address Translation36110.6.2.1.1 Inbound Address Translation36110.6.2.1.2 Outbound Address Translation36210.6.2.1.3 Base Address Register Overview36310.6.3 XL bus Arbitration Priority364Chapter 11 ATA Controller36611.1 Overview36611.2 BestComm Key Features36611.2.1 BestComm Read36611.2.2 BestComm Write36711.3 ATA Register Interface36711.3.1 ATA Host Registers-MBAR + 0x3A0036711.3.1.1 ATA Host Configuration Register-MBAR + 0x3A0036711.3.1.2 ATA Host Status Register-MBAR + 0x3A0436811.3.1.3 ATA PIO Timing 1 Register-MBAR + 0x3A0836811.3.1.4 ATA PIO Timing 2 Register-MBAR + 0x3A0C36911.3.1.5 ATA Multiword DMA Timing 1 Register-MBAR + 0x3A1036911.3.1.6 ATA Multiword DMA Timing 2 Register-MBAR + 0x3A1437011.3.1.7 ATA Ultra DMA Timing 1 Register-MBAR + 0x3A1837011.3.1.8 ATA Ultra DMA Timing 2 Register-MBAR + 0x3A1C37111.3.1.9 ATA Ultra DMA Timing 3 Register-MBAR + 0x 3A2037111.3.1.10 ATA Ultra DMA Timing 4 Register-MBAR + 0x3A2437211.3.1.11 ATA Ultra DMA Timing 5 Register-MBAR + 0x3A2837311.3.1.12 ATA Share Count Register-MBAR + 0x3A2C37311.3.2 ATA FIFO Registers-MBAR + 0x3A0037311.3.2.1 ATA Rx / Tx FIFO Data Word Register-MBAR + 0x3A3C37411.3.2.2 ATA Rx / Tx FIFO Status Register-MBAR + 0x3A4037411.3.2.3 ATA Rx / Tx FIFO Control Register-MBAR + 0x3A4437511.3.2.4 ATA Rx / Tx FIFO Alarm Register-MBAR + 0x3A4837511.3.2.5 ATA Rx / Tx FIFO Read Pointer Register-MBAR + 0x3A4C37611.3.2.6 ATA Rx / Tx FIFO Write Pointer Register-MBAR + 0x3A5037611.3.3 ATA Drive Registers-MBAR + 0x3A0037711.3.3.1 ATA Drive Device Control Register-MBAR + 0x3A5C37711.3.3.2 ATA Drive Alternate Status Register-MBAR + 0x3A5C37811.3.3.3 ATA Drive Data Register-MBAR + 0x3A6037811.3.3.4 ATA Drive Features Register-MBAR + 0x3A6437911.3.3.5 ATA Drive Error Register-MBAR + 0x3A6437911.3.3.6 ATA Drive Sector Count Register-MBAR + 0x3A6838011.3.3.7 ATA Drive Sector Number Register-MBAR + 0x3A6C38011.3.3.8 ATA Drive Cylinder Low Register-MBAR + 0x3A7038111.3.3.9 ATA Drive Cylinder High Register-MBAR + 0x3A7438111.3.3.10 ATA Drive Device / Head Register-MBAR + 0x3A7838211.3.3.11 ATA Drive Device Command Register-MBAR + 0x3A7C38211.3.3.12 ATA Drive Device Status Register-MBAR + 0x3A7C38411.4 ATA Host Controller Operation38511.4.1 PIO State Machine38611.4.2 DMA State Machine38711.4.2.1 Software Requirements38711.5 Signals and Connections38811.6 ATA Interface Description38911.7 ATA Bus Background39111.7.1 Terminology39111.7.2 ATA Modes39211.7.3 ATA Addressing39211.7.3.1 ATA Register Addressing39311.7.3.2 Drive Interrupt39311.7.3.3 Sector Addressing39311.7.3.4 Physical / Logical Addressing Modes39411.7.4 ATA Transactions39511.7.4.1 PIO Mode Transactions39511.7.4.1.1 Class 1-PIO Read39511.7.4.1.2 Class 2-PIO Write39611.7.4.1.3 Class 3-Non-Data Command39711.7.4.2 DMA Protocol39711.7.4.3 Multiword DMA Transactions40011.7.4.3.1 Class 4-DMA Command40011.7.4.4 Ultra DMA Protocol40011.8 ATA RESET / Power-Up40111.8.1 Hardware Reset40111.8.2 Software Reset40111.9 ATA I/O Cable Specifications402Chapter 12 Universal Serial Bus ( USB )40412.1 Overview40412.2 Data Transfer Types40412.3 Host Controller Interface40512.3.1 Communication Channels40512.3.2 Data Structures40612.4 Host Control ( HC ) Operational Registers40812.4.1 Programming Note40812.4.2 Control and Status Partition-MBAR + 0x100040912.4.2.1 USB HC Revision Register-MBAR + 0x100040912.4.2.2 USB HC Control Register-MBAR + 0x100440912.4.2.3 USB HC Command Status Register-MBAR + 0x100841112.4.2.4 USB HC Interrupt Status Register -MBAR + 0x 100C41212.4.2.5 USB HC Interrupt Enable Register-MBAR + 0x 101041312.4.2.6 USB HC Interrupt Disable Register-MBAR + 0x 101441412.4.3 Memory Pointer Partition-MBAR + 0x101841512.4.3.1 USB HC HCCA Register-MBAR + 0x101841612.4.3.2 USB HC Period Current Endpoint Descriptor Register -MBAR + 0x101C41612.4.3.3 USB HC Control Head Endpoint Descriptor Register -MBAR + 0x102041712.4.3.4 USB HC Control Current Endpoint Descriptor Register -MBAR + 0x102441712.4.3.5 USB HC Bulk Head Endpoint Descriptor Register-MBAR + 0x102841712.4.3.6 USB HC Bulk Current Endpoint Descriptor Register-MBAR + 0x102C41812.4.3.7 USB HC Done Head Register-MBAR + 0x103041812.4.4 Frame Counter Partition-MBAR + 0x103441912.4.4.1 USB HC Frame Interval Register-MBAR + 0x103441912.4.4.2 USB HC Frame Remaining Register-MBAR + 0x103842012.4.4.3 USB HC Frame Number Register-MBAR + 0x103C42012.4.4.4 USB HC Periodic Start Register-MBAR + 0x104042112.4.4.5 USB HC LS Threshold Register-MBAR + 0x104442112.4.5 Root Hub Partition-MBAR + 0x104842212.4.5.1 USB HC Rh Descriptor A Register-MBAR + 0x104842212.4.5.2 USB HC Rh Descriptor B Register-MBAR + 0x104C42312.4.5.3 USB HC Rh Status Register-MBAR + 0x105042412.4.5.4 USB HC Rh Port1 Status Register-MBAR + 0x105442512.4.5.5 USB HC Rh Port2 Status Register-MBAR + 0x1058429Chapter 13 BestComm43413.1 Overview43413.2 BestComm Functional Description43413.3 Features summary43513.4 Descriptors43513.5 Tasks43513.6 Memory Map/ Register Definitions43513.7 Task Table (Entry Table)43613.8 Task Descriptor Table43613.9 Variable Table43613.10 Function Descriptor Table43613.11 Context Save Area43613.12 External DMA Request43613.13 External DMA Breakpoint43613.14 BestComm XLB Address Snooping43713.15 BestComm DMA Registers-MBAR + 0x120043713.15.1 SDMA Task Bar Register-MBAR + 0x120043713.15.2 SDMA Current Pointer Register-MBAR + 0x120443813.15.3 SDMA End Pointer Register-MBAR + 0x120843813.15.4 SDMA Variable Pointer Register-MBAR + 0x120C43813.15.5 SDMA Interrupt Vector, PTD Control Register-MBAR + 0x121043913.15.6 SDMA Interrupt Pending Register-MBAR + 0x121444013.15.7 SDMA Interrupt Mask Register-MBAR + 0x121844113.15.8 SDMA Task Control 0 Register-MBAR + 0x121C44213.15.9 SDMA Task Control 2 Register-MBAR + 0x122044313.15.10 SDMA Task Control 4 Register-MBAR + 0x122444413.15.11 SDMA Task Control 6 Register-MBAR + 0x122844413.15.12 SDMA Task Control 8 Register-MBAR + 0x122C44513.15.13 SDMA Task Control A Register-MBAR + 0x123044513.15.14 SDMA Task Control C Register-MBAR + 0x123444613.15.15 SDMA Task Control E Register-MBAR + 0x123844613.15.16 SDMA Initiator Priority 0 Register-MBAR + 0x123C44713.15.17 SDMA Initiator Priority 4 Register-MBAR + 0x124044813.15.18 SDMA Initiator Priority 8 Register-MBAR + 0x124444813.15.19 SDMA Initiator Priority 12 Register-MBAR + 0x124844913.15.20 SDMA Initiator Priority 16 Register-MBAR + 0x124C45013.15.21 SDMA Initiator Priority 20 Register-MBAR + 0x125045113.15.22 SDMA Initiator Priority 24 Register-MBAR + 0x125445113.15.23 SDMA Initiator Priority 28 Register-MBAR + 0x125845213.15.24 SDMA Requestor MuxControl-MBAR + 0x125C45313.15.25 SDMA task Size0-MBAR + 0x126045513.15.26 SDMA task 0 & task Size 1 map45613.15.27 SDMA Reserved Register 1-MBAR + 0x126845613.15.28 SDMA Reserved Register 2-MBAR + 0x126C45713.15.29 SDMA Debug Module Comparator 1, Value 1 Register-MBAR + 0x127045713.15.30 SDMA Debug Module Comparator 2, Value 2 Register-MBAR + 0x127445713.15.31 SDMA Debug Module Control Register-MBAR + 0x127845813.15.32 SDMA Debug Module Status Register-MBAR + 0x127C46013.16 On-Chip SRAM46113.17 Programming Model46113.17.1 Task Table46113.17.1.1 Integer Mode46313.17.1.2 Pack46313.17.2 Variable Table463Chapter 14 Fast Ethernet Controller ( FEC )46614.1 Overview46614.1.1 Features46714.2 Modes of Operation46814.2.1 Full- and Half-Duplex Operation46814.2.2 10 Mbps and 100 Mbps MII Interface Operation46814.2.3 10 Mbps 7-Wire Interface Operation46814.2.4 Address Recognition Options46814.2.5 Internal Loopback46814.3 I / O Signal Overview46814.3.1 Detailed Signal Descriptions46914.3.1.1 MII Ethernet MAC-PHY Interface46914.3.1.2 MII Management Frame Structure47014.3.1.2.1 MII Management Register Set47114.4 FEC Memory Map and Registers47114.4.1 Control and Status (CSR) Memory Map47214.4.2 MIB Block Counters Memory Map47314.5 FEC Registers-MBAR + 0x300047514.5.1 FEC ID Register-MBAR + 0x300047614.5.2 FEC Interrupt Event Register-MBAR + 0x300447714.5.3 FEC Interrupt Enable Register-MBAR + 0x300847914.5.4 FEC Rx Descriptor Active Register-MBAR + 0x301047914.5.5 FEC Tx Descriptor Active Register-MBAR + 0x301448014.5.6 FEC Ethernet Control Register-MBAR + 0x302448114.5.7 FEC MII Management Frame Register-MBAR + 0x304048214.5.8 FEC MII Speed Control Register-MBAR + 0x304448314.5.9 FEC MIB Control Register-MBAR + 0x306448414.5.10 FEC Receive Control Register-MBAR + 0x308448514.5.11 FEC Hash Register-MBAR + 0x308848614.5.12 FEC Tx Control Register-MBAR + 0x30C448614.5.13 FEC Physical Address Low Register-MBAR + 0x30E448714.5.14 FEC Physical Address High Register-MBAR + 0x30E848814.5.15 FEC Opcode / Pause Duration Register-MBAR + 0x30EC48814.5.16 FEC Descriptor Individual Address 1 Registe-MBAR + 0x311848914.5.17 FEC Descriptor Individual Address 2 Register-MBAR + 0x311C48914.5.18 FEC Descriptor Group Address 1 Register-MBAR + 0x312049014.5.19 FEC Descriptor Group Address 2 Register-MBAR + 0x312449014.5.20 FEC Tx FIFO Watermark Register-MBAR + 0x314449114.6 FIFO Interface49214.6.1 FEC Rx FIFO Data Register-MBAR + 0x318449314.7 FEC Tx FIFO Data Register-MBAR + 0x31A449314.7.1 FEC Rx FIFO Status Register-MBAR + 0x318849314.8 FEC Tx FIFO Status Register-MBAR + 0x31A849314.8.1 FEC Rx FIFO Control Register-MBAR + 0x318C49414.8.2 FEC Rx FIFO Last Read Frame Pointer Register-MBAR + 0x319049514.8.3 FEC Rx FIFO Last Write Frame Pointer Register-MBAR + 0x319449614.8.4 FEC Rx FIFO Alarm Pointer Register-MBAR + 0x319849614.8.5 FEC Rx FIFO Read Pointer Register-MBAR + 0x319C49714.8.6 FEC Rx FIFO Write Pointer Register-MBAR + 0x31A049814.8.7 FEC Reset Control Register-MBAR + 0x31C449814.8.8 FEC Transmit FSM Register-MBAR + 0x31C849914.9 Initialization Sequence49914.9.1 Hardware Controlled Initialization49914.9.2 User Initialization (Prior to Asserting ETHER_EN)50014.9.2.1 Microcontroller Initialization50014.9.3 Frame Control/Status Words50014.9.3.1 Receive Frame Status Word50014.9.3.2 Transmit Frame Control Word50114.9.4 Network Interface Options50214.9.5 FEC Frame Reception50214.9.6 Ethernet Address Recognition50314.9.7 Full-Duplex Flow Control50714.9.8 Inter-Packet Gap Time50814.9.9 Collision Handling50814.9.10 Internal and External Loopback50914.9.11 Ethernet Error-Handling Procedure50914.9.11.1 Transmission Errors50914.9.11.2 Reception Errors509Chapter 15 Programmable Serial Controller ( PSC)51215.1 Overview51215.1.1 PSC Functions Overview51315.1.2 Features51415.2 PSC Registers-MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0051515.2.1 Mode Register 1 (0x00)-MR151615.2.2 Mode Register 2 (0x00) - MR251815.2.3 Status Register (0x04) - SR51915.2.4 Clock Select Register (0x04) - CSR52315.2.5 Command Register (0x08)-CR52315.2.6 Rx Buffer Register (0x0C) - RB52615.2.7 Tx Buffer Register (0x0C)-TB52715.2.8 Input Port Change Register (0x10) - IPCR52815.2.9 Auxiliary Control Register (0x10) - ACR52915.2.10 Interrupt Status Register (0x14) - ISR53015.2.11 Interrupt Mask Register (0x14)-IMR53115.2.12 Counter Timer Upper Register (0x18)-CTUR53315.2.13 Counter Timer Lower Register (0x1C)-CTLR53415.2.14 Codec Clock Register (0x20)-CCR53415.2.15 AC97 Slots Register (0x24)-AC97Slots53715.2.16 AC97 Command Register (0x28)-AC97CMD53715.2.17 AC97 Status Data Register (0x2C)-AC97Data53815.2.18 Interrupt Vector Register (0x30)-IVR53815.2.19 Input Port Register (0x34)-IP53915.2.20 Output Port 1 Bit Set (0x38)-OP154015.2.21 Output Port 0 Bit Set (0x3C)-OP054015.2.22 Serial Interface Control Register (0x40)-SICR54115.2.23 Infrared Control 1 (0x44)-IRCR154415.2.24 Infrared Control 2 (0x48)-IRCR254415.2.25 Infrared SIR Divide Register (0x4C)-IRSDR54515.2.26 Infrared MIR Divide Register (0x50)-IRMDR54615.2.27 Infrared FIR Divide Register (0x54)-IRFDR54715.2.28 Rx FIFO Number of Data (0x58)-RFNUM54915.2.29 Tx FIFO Number of Data (0x5C)-TFNUM54915.2.30 Rx FIFO Data (0x60)-RFDATA54915.2.31 Rx FIFO Status (0x64)-RFSTAT54915.2.32 Rx FIFO Control (0x68)-RFCNTL55015.2.33 Rx FIFO Alarm (0x6E)-RFALARM55015.2.34 Rx FIFO Read Pointer (0x72)-RFRPTR55115.2.35 Rx FIFO Write Pointer(0x76)-RFWPTR55115.2.36 Rx FIFO Last Read Frame (0x7A)-RFLRFPTR55115.2.37 Rx FIFO Last Write Frame PTR (0x7C)-RFLWFPTR55215.2.38 Tx FIFO Data (0x80)-TFDATA55215.2.39 Tx FIFO Status (0x84)-TFSTAT55215.2.40 Tx FIFO Control (0x88)-TFCNTL55315.2.41 Tx FIFO Alarm (0x8E)-TFALARM55315.2.42 Tx FIFO Read Pointer (0x92)-TFRPTR55315.2.43 Tx FIFO Write Pointer (0x96)-TFWPTR55415.2.44 Tx FIFO Last Read Frame (0x9A)-TFLRFPTR55415.2.45 Tx FIFO Last Write Frame PTR (0x9C)-TFLWFPTR55415.3 PSC Operation Modes55515.3.1 PSC in UART Mode55515.3.1.1 Block Diagram and Signal Definition for UART Mode55515.3.1.2 UART Clock Generation55715.3.1.3 Transmitting in UART Mode55715.3.1.4 Receiving in UART Mode55815.3.1.5 Configuration Sequence for UART Mode55915.3.2 PSC in Codec Mode56015.3.2.1 Block Diagram and Signal Definition for Codec Mode56115.3.2.2 Codec Clock and FrameSync Generation56215.3.2.3 Transmitting and Receiving in “Soft Modem” Codec Mode56315.3.2.4 Transmitting and Receiving in ESAI Mode (Enhanced Serial Audio Interface)56515.3.2.5 Transmitting and Receiving in “Cell Phone” Mode56715.3.2.6 Transmitting and Receiving in I2S Master Mode56815.3.2.7 Transmitting and Receiving in SPI Mode57015.3.3 PSC in AC97 Mode57215.3.3.1 Block Diagram and Signal Definition for AC97 Mode57315.3.3.2 Generate a reset pulse for the external AC97 Codec device57415.3.3.3 AC97 Low-Power Mode57415.3.3.4 Transmitting and Receiving in “Normal” AC97 Mode57515.3.3.5 Transmitting and Receiving in “Enhanced” AC97 Mode57515.3.4 PSC in IrDA mode57615.3.4.1 PSC in SIR Mode57615.3.4.1.1 Block Diagram and Signal Definition for SIR Mode57615.3.4.1.2 Transmitting and Receiving in SIR Mode57715.3.4.1.3 Configuration Sequence Example for SIR Mode57815.3.4.2 PSC in MIR Mode57815.3.4.2.1 Block Diagram and Signal Definition for MIR Mode57815.3.4.2.2 Transmitting and Receiving in MIR Mode57915.3.4.2.3 Serial Interaction Pulse (SIP)58015.3.4.2.4 Configuration Sequence Example for MIR Mode58015.3.4.3 PSC in FIR Mode58115.3.4.3.1 Block Diagram and Signal Definition for FIR Mode58115.3.4.3.2 Transmitting and Receiving in FIR Mode58115.3.4.3.3 Configuration Sequence Example for FIR Mode58215.4 PSC FIFO System58215.4.1 RX FIFO58415.4.2 TX FIFO58515.4.3 Looping Modes58515.4.3.1 Automatic Echo Mode58515.4.3.2 Local Loop-Back Mode58515.4.3.3 Remote Loop-Back Mode58615.4.4 Multidrop Mode586Chapter 16 XLB Arbiter58816.1 Overview58816.1.1 Purpose58816.1.1.1 Prioritization58816.1.1.2 Bus Grant Mechanism58916.1.1.2.1 Bus Grant58916.1.1.2.2 Parking Modes58916.1.1.3 Configuration, Status, and Interrupt Generation58916.1.1.4 Watchdog Functions58916.1.1.4.1 Timer Functions58916.1.1.4.2 Other Tenure Ending Conditions59016.2 XLB Arbiter Registers-MBAR + 0x1F0059016.2.1 Arbiter Configuration Register (R/W)-MBAR + 0x1F4059016.2.2 Arbiter Version Register (R)-MBAR + 0x1F4459216.2.3 Arbiter Status Register (R/W)-MBAR + 0x1F4859216.2.4 Arbiter Interrupt Enable Register (R/W)-MBAR + 0x1F4C59316.2.5 Arbiter Address Capture Register (R)-MBAR + 0x1F5059416.2.6 Arbiter Bus Signal Capture Register (R)-MBAR + 0x1F5459516.2.7 Arbiter Address Tenure Time-Out Register (R/W)-MBAR + 0x1F5859516.2.8 Arbiter Data Tenure Time-Out Register (R/W)-MBAR + 0x1F5C59616.2.9 Arbiter Bus Activity Time-Out Register (R/W)-MBAR + 0x1F6059616.2.10 Arbiter Master Priority Enable Register (R/W)-MBAR + 0x1F6459716.2.11 Arbiter Master Priority Register (R/W)-MBAR + 0x1F6859816.2.12 Arbiter Snoop Window Register (RW)-MBAR + 0x1F7059916.2.13 Arbiter Reserved Registers-MBAR + 0x1F00-1F3C, 0x1F74-1FFF600Chapter 17 Serial Peripheral Interface ( SPI )60217.1 Overview60217.1.1 Features60217.1.2 Modes of Operation60317.2 SPI Signal Description60317.2.1 Master In / Slave Out ( MISO )60317.2.2 Master Out / Slave In ( MOSI )60317.2.3 Serial Clock ( SCK )60317.2.4 Slave-Select ( SS )60317.3 SPI Registers-MBAR + 0x0F0060417.3.1 SPI Control Register 1-MBAR + 0x0F0060417.3.2 SPI Control Register 2-MBAR + 0x0F0160517.3.3 SPI Baud Rate Register-MBAR + 0x0F0460617.3.4 SPI Status Register -MBAR + 0x0F0560717.3.5 SPI Data Register-MBAR + 0x0F0960817.3.6 SPI Port Data Register-MBAR + 0x0F0D60817.3.7 SPI Data Direction Register-MBAR + 0x0F1060817.4 Functional Description60917.4.1 General60917.4.2 Master Mode60917.4.3 Slave Mode61017.4.4 Transmission Formats61017.4.4.1 Clock Phase and Polarity Controls61117.4.4.2 CPHA = 0 Transfer Format61117.4.4.3 CPHA = 1 Transfer Format61217.4.5 SPI Baud Rate Generation61317.4.6 Special Features61417.4.6.1 SS Output61417.4.6.2 Bidirectional Mode (MOMI or SISO)61417.4.7 Error Conditions61517.4.7.1 Write Collision Error61517.4.7.2 Mode Fault Error61517.4.8 Low Power Mode Options61517.4.8.1 SPI in Run Mode61517.4.8.2 SPI in Wait Mode61517.4.8.3 SPI in Stop Mode61617.4.9 SPI Interrupts61617.4.9.1 MODF Description61617.4.9.2 SPIF Description616Chapter 18 Inter-Integrated Circuit ( I 2 C )61818.1 Overview61818.1.1 Features61818.2 I2C Controller61918.2.1 START Signal61918.2.2 STOP Signal61918.2.2.1 Slave Address Transmission62018.2.2.2 Data Transfer62018.2.2.3 Acknowledge62018.2.2.4 Repeated Start62118.2.2.5 Clock Synchronization and Arbitration62118.3 I2C Interface Registers62218.3.1 I2C Address Register (MADR)-MBAR + 0x3D00 / 0x3D4062318.3.2 I2C Frequency Divider Register (MFDR)-MBAR + 0x3D04 / 0x3D4462318.3.3 I2C Control Register (MCR)-MBAR + 0x3D08 / 0x3D4863018.3.4 I2C Status Register (MSR)-MBAR + 0x3D0C / 0x3D4C63218.3.5 I2C Data I / O Register (MDR)-MBAR+ x3D10 / 0x3D5063318.3.6 I2C Interrupt Control Register-MBAR + 0x3D2063418.3.7 I2C Filter Register (MIFR)-MBAR + 0x3D2463518.4 Initialization Sequence63618.5 Transfer Initiation and Interrupt63618.5.1 Post-Transfer Software Response63618.5.2 Slave Mode63618.5.3 Special Note on AKF637Chapter 19 Controller Area Network ( MSCAN )64019.1 Overview64019.2 Features64119.3 External Signals64119.3.1 RXCAN - CAN Receiver Input Pin64119.3.2 TXCAN - CAN Transmitter Output Pin64119.4 CAN System64119.5 Memory Map / Register Definition64219.5.1 Module Memory Map64219.5.2 Register Descriptions64419.5.3 MSCAN Control Register 0 (CANCTL0)-MBAR + 0x0900 / 0x98064419.5.4 MSCAN Control Register 1 (CANCTL1)-MBAR + 0x0901 / 0x98164619.5.5 MSCAN Bus Timing Register 0 (CANBTR0)-MBAR + 0x0904 / 0x98464719.5.6 MSCAN Bus Timing Register 1 (CANBTR1)-MBAR + 0x0905 / 0x98564819.5.7 MSCAN Receiver Flag Register (CANRFLG)-MBAR+0x0908 / 0x98864919.5.8 MSCAN Receiver Interrupt Enable Register (CANRIER)-MBAR + 0x0909 / 0x98965119.5.9 MSCAN Transmitter Flag Register (CANTFLG)-MBAR + 0x090C / 0x98C65219.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)-MBAR+0x090D / 0x098D65319.5.11 MSCAN Transmitter Message Abort Request (CANTARQ)-MBAR + 0x0910 / 0x099065319.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)-MBAR +0x0911 / 0x099165419.5.13 MSCAN Transmit Buffer Selection (CANTBSEL)-MBAR + 0x0914 /0x099165419.5.14 MSCAN ID Acceptance Control Register (CANIDAC)-MBAR + 0x0915 / 0x099565519.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C65619.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D65619.5.17 MSCAN ID Acceptance Registers (CANIDAR0-7)-MBAR + 0x0920 / 0x09A065719.5.18 MSCAN ID Mask Register (CANIDMR0-7)-MBAR + 0x0928 / 0x09A865919.6 Programmer’s Model of Message Storage66119.6.1 Identifier Registers (IDR0-3)66319.6.2 Data Segment Registers (DSR0-7)66319.6.3 Data Length Register (DLR)66419.6.4 MSCAN Transmit Buffer Priority Register (TBPR)-MBAR + 0x0979 / 0x09F966419.6.5 MSCAN Time Stamp Register High (TSRH)-MBAR + 0x097C / 0x09FC66519.6.6 MSCAN Time Stamp Register Low (TSRL)-MBAR + 0x097D / 0x09FD66519.7 Functional Description66519.7.1 General66519.7.2 Message Storage66619.7.2.1 Message Transmit Background66619.7.2.2 Transmit Structures66719.7.2.3 Receive Structures66719.7.3 Identifier Acceptance Filter66819.7.4 Protocol Violation Protection67019.7.5 Clock System67119.7.6 Timer Link67319.7.7 Modes of Operation67319.7.7.1 Normal Modes67319.7.7.2 Listen-Only Mode67319.7.8 Low Power Options67319.7.8.1 CPU Run Mode67419.7.8.2 CPU Sleep Mode67419.7.8.3 CPU Deep Sleep Mode67419.7.8.4 MSCAN Sleep Mode67419.7.8.5 MSCAN Initialization Mode67519.7.8.6 MSCAN Power Down Mode67619.7.8.7 Programmable Wake-Up Function67619.7.9 Description of Interrupt Operation67619.7.9.1 Transmit Interrupt67719.7.9.2 Receive Interrupt67719.7.9.3 Wake-Up Interrupt67719.7.9.4 Error Interrupt67819.7.10 Interrupt Acknowledge67819.7.11 Recovery from STOP or WAIT678Chapter 20 Byte Data Link Controller (BDLC)68020.1 Overview68020.2 Features68020.3 Modes of Operation68020.4 Block Diagram68320.5 Signal Description68420.6 Overview68420.6.1 Detailed Signal Descriptions68420.6.1.1 TXB - BDLC Transmit Pin68420.6.1.2 RXB - BDLC Receive Pin68420.7 Memory Map and Registers68420.7.1 Overview68420.7.2 Module Memory Map68420.7.3 Register Descriptions68420.7.3.1 BDLC Control Register 1 (DLCBCR1)-MBAR + 0x130068420.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x130068620.7.3.3 BDLC Control Register 2 (DLCBCR2) - MBAR + 0x130468720.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x130569120.7.3.5 BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0x130869120.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x130969320.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C69420.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D69420.8 Functional Description69520.8.1 General69520.8.1.1 J1850 Frame Format69520.8.1.2 J1850 VPW Symbols69620.8.1.3 J1850 VPW Valid/Invalid Bits & Symbols69820.8.1.4 J1850 Bus Errors70520.8.2 Mux Interface70620.8.2.1 Mux Interface - Rx Digital Filter70620.8.3 Protocol Handler70720.8.3.1 Protocol Architecture70820.8.4 Transmitting A Message70920.8.4.1 BDLC Transmission Control Bits70920.8.4.2 Transmitting Exceptions71020.8.4.3 Aborting a Transmission71120.8.5 Receiving A Message71220.8.5.1 BDLC Reception Control Bits71320.8.5.2 Receiving a Message with the BDLC module71320.8.5.3 Filtering Received Messages71320.8.5.4 Receiving Exceptions71320.8.6 Transmitting An In-Frame Response (IFR)71520.8.6.1 IFR Types Supported by the BDLC module71620.8.6.2 BDLC IFR Transmit Control Bits71620.8.6.3 Transmit Single Byte IFR71720.8.6.4 Transmit Multi-Byte IFR 171720.8.6.5 Transmit Multi-Byte IFR 071720.8.6.6 Transmitting An IFR with the BDLC module71720.8.6.7 Transmitting IFR Exceptions72120.8.7 Receiving An In-Frame Response (IFR)72220.8.7.1 Receiving an IFR with the BDLC module72320.8.7.2 Receiving IFR Exceptions72420.8.8 Special BDLC Module Operations72420.8.8.1 Transmitting Or Receiving A Block Mode Message72420.8.8.2 Transmitting Or Receiving A Message In 4X Mode72520.8.9 BDLC Module Initialization72620.8.9.1 Initialization Sequence72620.8.9.2 Initializing the Configuration Bits72720.8.9.3 Exiting Loopback Mode and Enabling the BDLC module72720.8.9.4 Enabling BDLC Interrupts72720.9 Resets72920.9.1 General729Chapter 21 Debug Support and JTAG Interface73021.1 Overview73021.2 TAP Link Module (TLM) and Slave TAP Implementation73021.3 TLM and TAP Signal Descriptions73321.3.1 Test Reset ( TRST )73321.3.2 Test Clock ( TCK )73321.3.3 Test Mode Select ( TMS )73321.3.4 Test Data In ( TDI )73321.3.5 Test Data Out ( TDO )73421.4 Slave Test Reset ( STRST )73421.4.1 Enable Slave-ENA [ 0 : n ]73421.4.2 Select DR Link-SEL [ 0 : n ]73421.4.3 Slave Test Data Out-STDO [ 0 : n ]73421.5 TAP State Machines73421.6 e300 Core JTAG / COP Serial Interface73521.7 TLM Link DR Instructions73621.7.1 TLM : TLMENA73721.7.2 TLM : PPCENA73721.8 TLM Test Instructions73721.8.1 IDCODE73721.8.1.1 Device ID Register73721.8.2 BYPASS73721.8.3 SAMPLE / PRELOAD73721.8.4 EXTEST73821.8.5 CLAMP73821.8.6 HIGHZ73821.9 e300 COP / BDM Interface738Appendix A Acronyms and Terms740Appendix B List of Registers752Размер: 4,6 МБСтраницы: 762Язык: EnglishПросмотреть
