Инструкции для Fujitsu Xeon

Содержание

• 1.0 Introduction

  9
  • 1.1 Terminology

    10
  • 1.2 References

    12
  • 1.3 State of Data

    12
• 2.0 Electrical Specifications

  13
  • 2.1 Power and Ground Pins

    13
  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 VCC Decoupling

      13
    • 2.2.2 VTT Decoupling

      13
    • 2.2.3 Front Side Bus AGTL+ Decoupling

      13
  • 2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

    14
    • 2.3.1 Front Side Bus Frequency Select Signals (BSEL[1:0])

      14
    • 2.3.2 Phase Lock Loop (PLL) and Filter

      15
  • 2.4 Voltage Identification (VID)

    15
  • 2.5 Reserved or Unused Pins

    17
  • 2.6 Front Side Bus Signal Groups

    18
  • 2.7 GTL+ Asynchronous and AGTL+ Asynchronous Signals

    20
  • 2.8 Test Access Port (TAP) Connection

    21
  • 2.9 Mixing Processors

    21
  • 2.10 Absolute Maximum and Minimum Ratings

    21
  • 2.11 Processor DC Specifications

    22
    • 2.11.1 Flexible Motherboard Guidelines (FMB)

      22
    • 2.11.2 VCC Overshoot Specification

      27
    • 2.11.3 Die Voltage Validation

      28
• 3.0 Mechanical Specifications

  31
  • 3.1 Package Mechanical Drawings

    31
  • 3.2 Processor Component Keepout Zones

    34
  • 3.3 Package Loading Specifications

    34
  • 3.4 Package Handling Guidelines

    35
  • 3.5 Package Insertion Specifications

    35
  • 3.6 Processor Mass Specifications

    35
  • 3.7 Processor Materials

    35
  • 3.8 Processor Markings

    36
  • 3.9 Processor Pinout Coordinates

    37
• 4.0 Signal Definitions

  39
  • 4.1 Signal Definitions

    39
• 5.0 Pin List

  49
  • 5.1 Intel® Xeon™ Processor with 800 MHz System Bus Pin Assignments

    49
    • 5.1.1 Pin Listing by Pin Name

      50
    • 5.1.2 Pin Listing by Pin Number

      58
• 6.0 Thermal Specifications

  67
  • 6.1 Package Thermal Specifications

    67
    • 6.1.1 Thermal Specifications

      67
    • 6.1.2 Thermal Metrology

      71
  • 6.2 Processor Thermal Features

    71
    • 6.2.1 Thermal Monitor

      71
    • 6.2.2 On-Demand Mode

      72
    • 6.2.3 PROCHOT# Signal Pin

      72
    • 6.2.4 FORCEPR# Signal Pin

      72
    • 6.2.5 THERMTRIP# Signal Pin

      73
    • 6.2.6 TCONTROL and Fan Speed Reduction

      73
    • 6.2.7 Thermal Diode

      73
• 7.0 Features

  75
  • 7.1 Power-On Configuration Options

    75
  • 7.2 Clock Control and Low Power States

    75
    • 7.2.1 Normal State

      76
    • 7.2.2 HALT Power-Down State

      76
    • 7.2.3 Stop-Grant State

      76
    • 7.2.4 HALT Snoop State or Snoop State

      77
    • 7.2.5 Sleep State

      77
  • 7.3 Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technology

    78
• 8.0 Boxed Processor Specifications

  79
  • 8.1 Introduction

    79
  • 8.2 Mechanical Specifications

    81
    • 8.2.1 Boxed Processor Heatsink Dimensions (CEK)

      81
    • 8.2.2 Boxed Processor Heatsink Weight

      89
    • 8.2.3 Boxed Processor Retention Mechanism and Heatsink Support (CEK)

      89
  • 8.3 Electrical Requirements

    89
    • 8.3.1 Fan Power Supply (active CEK)

      89
  • 8.4 Thermal Specifications

    92
    • 8.4.1 Boxed Processor Cooling Requirements

      92
  • 8.5 Boxed Processor Contents

    93
• 9.0 Debug Tools Specifications

  95
  • 9.1 Debug Port System Requirements

    95
  • 9.2 Target System Implementation

    95
    • 9.2.1 System Implementation

      95
  • 9.3 Logic Analyzer Interface (LAI)

    95
    • 9.3.1 Mechanical Considerations

      96
    • 9.3.2 Electrical Considerations

      96