Техническая Спецификация (RH80532NC029256)СодержаниеIntroduction10Overview10State of the Data11Terminology11References12Mobile Intel Celeron Processor Features13New Features in the Mobile Intel Celeron Processor132.1.1 133-MHz PSB With AGTL Signaling132.1.2 256-K On-die Integrated L2 Cache132.1.3 Data Prefetch Logic132.1.4 Differential Clocking13(0.13 µ) (in Micro-FCBGA and Micro-FCPGA Packages)14Power Management142.2.1 Clock Control Architecture142.2.2 Normal State142.2.3 Auto Halt State14Table 1. New and Revised Mobile Intel Celeron Processor (0.13 µ) Signals142.2.4 Quick Start State15Figure 1. Clock Control States152.2.5 HALT/Grant Snoop State162.2.6 Deep Sleep State162.2.7 Operating System Implications of Low-power States17AGTL Signals17Mobile Intel Celeron Processor CPUID17Table 2. Clock State Characteristics17Table 3. Mobile Intel Celeron Processor CPUID18Table 4. Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors18Electrical Specifications19Processor System Signals19Table 5. System Signal Groups193.1.1 Power Sequencing Requirements203.1.2 Test Access Port (TAP) Connection20Table 6. Recommended Resistors for Mobile Intel Celeron Processor Signals203.1.3 Catastrophic Thermal Protection213.1.4 Unused Signals213.1.5 Signal State in Low-power States21System Bus Signals21CMOS and Open-drain Signals21Other Signals22Power Supply Requirements223.2.1 Decoupling Guidelines223.2.2 Voltage Planes223.2.3 Voltage Identification23Figure 2. PLL RLC Filter23Table 7. Mobile Intel Celeron Processor VID Values233.2.4 VTTPWRGD Signal Quality Specification24Transition Region24Transition Time24Figure 3. VTTPWRGD System-Level Connections24Table 8. VTTPWRGD Noise Specification24Table 9. VTTPWRGD Transition Time Specification24Noise25System Bus Clock and Processor Clocking25Figure 4. Noise Estimation25Maximum Ratings26DC Specifications26Table 10. Mobile Intel Celeron Processor Absolute Maximum Ratings26Table 11. Power Specifications for Mobile Intel Celeron Processor127VID = 1.15 V28Sleep State: VID = 1.15 V29VID = 1.1 V29in the Deep Sleep State: VID = 1.1 V30Table 16. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.40 V31VID = 1.40 V32Table 18. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.45 V33VID = 1.45 V34Table 20. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.50 V35VID = 1.50 V36Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.15 V)37Setting = 1.15 V)37Figure 7. Illustration of VCC Static and Transient Tolerances (VID = 1.40 V)38Setting = 1.40 V)39Table 22. AGTL Signal Group DC Specifications40Table 23. AGTL Bus DC Specifications40AC Specifications413.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications41Table 25. System Bus Clock AC Specifications (Differential)42Table 26. System Bus Clock AC Specifications (133 MHz, Single Ended)43Table 27. System Bus Clock AC Specifications (100 MHz, Single Ended)43Table 28. Valid Mobile Intel Celeron Processor Frequencies44Table 29. AGTL Signal Groups AC Specifications45Table 30. CMOS and Open-drain Signal Groups AC Specifications45Table 31. Reset Configuration AC Specifications and Power On/Power Down Timings46Table 32. APIC Bus Signal AC Specifications47Table 33. TAP Signal AC Specifications48Table 34. Quick Start/Deep Sleep AC Specifications48Figure 9. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform49Figure 10. Differential BCLK/BCLK# Waveform (Common Mode)49Figure 11. BCLK/BCLK# Waveform (Differential Mode)50Figure 12. Valid Delay Timings50Figure 13. Setup and Hold Timings51Figure 14. Cold/Warm Reset and Configuration Timings51Figure 15. Power-on Sequence and Reset Timings52Figure 16. Power Down Sequencing and Timings (VCC Leading)53Figure 17.Power Down Sequencing and Timings (VCCT Leading)54Figure 18.Test Timings (Boundary Scan)55Figure 19. Test Reset Timings55Figure 20.Quick Start/Deep Sleep Timing (BCLK Stopping Method)56Figure 21. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)57System Signal Simulations58Specifications58Table 35. BCLK (Differential) DC Specifications and AC Signal Quality Specifications58Table 36. BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications58Figure 22. BCLK (Single Ended)/PICCLK Generic Clock Waveform59Table 37. PICCLK DC Specifications and AC Signal Quality Specifications59AGTL AC Signal Quality Specifications60Figure 23. Maximum Acceptable Overshoot/Undershoot Waveform60Non-AGTL Signal Quality Specifications61Processor Core61Processor Core614.3.1 PWRGOOD, VTTPWRGD Signal Quality Specifications62VTTPWRGD Noise Parameter Specification62Core62Table 41. VTTPWRGD Noise Parameter Specification62VTTPWRGD Transition Parameter Recommendation63Transition Region63Transition Time63Noise63Table 42. VTTPWRGD Transition Parameter Recommendation63Figure 24. VTTPWRGD Noise Specification64Mechanical Specifications65Socketable Micro-FCPGA Package65Table 43. Socketable Micro-FCPGA Package Specification65Figure 25. Socketable Micro-FCPGA Package - Top and Bottom Isometric Views66Figure 26. Socketable Micro-FCPGA Package - Top and Side View67Figure 27. Socketable Micro-FCPGA Package - Bottom View68Surface Mount Micro-FCBGA Package69Table 44. Micro-FCBGA Package Mechanical Specifications69Figure 28. Micro-FCBGA Package – Top and Bottom Isometric Views70Figure 29. Micro-FCBGA Package – Top and Side Views71Figure 30. Micro-FCBGA Package - Bottom View72Signal Listings73Figure 31. Pin/Ball Map - Top View73Table 45. Signal Listing in Order by Pin/Ball Number74Table 46. Signal Listing in Order by Signal Name77Table 47. Voltage and No-Connect Pin/Ball Locations79VCC Thermal Specifications80Table 48. Power Specifications for Mobile Intel Celeron Processor81Thermal Diode82Table 49. Thermal Diode Interface82Table 50. Thermal Diode Specifications82Processor Initialization and Configuration83Description837.1.1 Quick Start Enable837.1.2 System Bus Frequency837.1.3 APIC Enable83Clock Frequencies and Ratios83Processor Interface84Alphabetical Signal Reference84Table 51. BSEL[1:0] Encoding86Signal Summaries94Table 52. Input Signals94Table 53. Output Signals94Table 54. Input/Output Signals (Single Driver)95Table 55. Input/Output Signals (Multiple Driver)95Appendix A. PLL RLC Filter Specification96Introduction96Filter Specification96Recommendation for Mobile Systems97Figure 32. PLL Filter Specifications97Table 56. PLL Filter Inductor Recommendations97Table 57. PLL Filter Capacitor Recommendations97Comments98Table 58. PLL Filter Resistor Recommendations98Размер: 1,9 МБСтраницы: 98Язык: EnglishПросмотреть