Инструкции для Intel X3460

Содержание

• 1 Introduction

  9
  • 1.1 Processor Feature Details

    11
    • 1.1.1 Supported Technologies

      11
  • 1.2 Interfaces

    11
    • 1.2.1 System Memory Support

      11
    • 1.2.2 PCI Express*

      12
    • 1.2.3 Direct Media Interface (DMI)

      13
    • 1.2.4 Platform Environment Control Interface (PECI)

      14
  • 1.3 Power Management Support

    14
    • 1.3.1 Processor Core

      14
    • 1.3.2 System

      14
    • 1.3.3 Memory Controller

      14
    • 1.3.4 PCI Express*

      14
  • 1.4 Thermal Management Support

    15
  • 1.5 Package

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  • 1.6 Terminology

    15
  • 1.7 Related Documents

    17
• 2 Interfaces

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  • 2.1 System Memory Interface

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    • 2.1.1 System Memory Technology Supported

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    • 2.1.2 System Memory Timing Support

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    • 2.1.3 System Memory Organization Modes

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      • 2.1.3.1 Single-Channel Mode

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      • 2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode

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    • 2.1.4 Rules for Populating Memory Slots

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    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

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      • 2.1.5.1 Just-in-Time Command Scheduling

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      • 2.1.5.2 Command Overlap

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      • 2.1.5.3 Out-of-Order Scheduling

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    • 2.1.6 System Memory Pre-Charge Power Down Support Details

      24
  • 2.2 PCI Express* Interface

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    • 2.2.1 PCI Express* Architecture

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      • 2.2.1.1 Transaction Layer

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      • 2.2.1.2 Data Link Layer

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      • 2.2.1.3 Physical Layer

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    • 2.2.2 PCI Express* Configuration Mechanism

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    • 2.2.3 PCI Express* Ports and Bifurcation

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      • 2.2.3.1 PCI Express* Bifurcated Mode

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  • 2.3 Direct Media Interface (DMI)

    28
    • 2.3.1 DMI Error Flow

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    • 2.3.2 Processor/PCH Compatibility Assumptions

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    • 2.3.3 DMI Link Down

      28
  • 2.4 Platform Environment Control Interface (PECI)

    29
  • 2.5 Interface Clocking

    29
    • 2.5.1 Internal Clocking Requirements

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• 3 Technologies

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  • 3.1 Intel® Virtualization Technology

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    • 3.1.1 Intel® VT-x Objectives

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    • 3.1.2 Intel® VT-x Features

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    • 3.1.3 Intel® VT-d Objectives

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    • 3.1.4 Intel® VT-d Features

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    • 3.1.5 Intel® VT-d Features Not Supported

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  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

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  • 3.3 Intel® Hyper-Threading Technology

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  • 3.4 Intel® Turbo Boost Technology

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• 4 Power Management

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  • 4.1 ACPI States Supported

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    • 4.1.1 System States

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    • 4.1.2 Processor Core/Package Idle States

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    • 4.1.3 Integrated Memory Controller States

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    • 4.1.4 PCI Express* Link States

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    • 4.1.5 Interface State Combinations

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  • 4.2 Processor Core Power Management

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    • 4.2.1 Enhanced Intel® SpeedStep® Technology

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    • 4.2.2 Low-Power Idle States

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    • 4.2.3 Requesting Low-Power Idle States

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    • 4.2.4 Core C-states

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      • 4.2.4.1 Core C0 State

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      • 4.2.4.2 Core C1/C1E State

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      • 4.2.4.3 Core C3 State

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      • 4.2.4.4 Core C6 State

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      • 4.2.4.5 C-State Auto-Demotion

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    • 4.2.5 Package C-States

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      • 4.2.5.1 Package C0

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      • 4.2.5.2 Package C1/C1E

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      • 4.2.5.3 Package C3 State

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      • 4.2.5.4 Package C6 State

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  • 4.3 IMC Power Management

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    • 4.3.1 Disabling Unused System Memory Outputs

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    • 4.3.2 DRAM Power Management and Initialization

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      • 4.3.2.1 Initialization Role of CKE

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      • 4.3.2.2 Conditional Self-Refresh

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      • 4.3.2.3 Dynamic Power Down Operation

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      • 4.3.2.4 DRAM I/O Power Management

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  • 4.4 PCI Express* Power Management

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• 5 Thermal Management

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• 6 Signal Description

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  • 6.1 System Memory Interface

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  • 6.2 Memory Reference and Compensation

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  • 6.3 Reset and Miscellaneous Signals

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  • 6.4 PCI Express* Based Interface Signals

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  • 6.5 DMI—Processor to PCH Serial Interface

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  • 6.6 PLL Signals

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  • 6.7 Intel® Flexible Display Interface Signals

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  • 6.8 JTAG/ITP Signals

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  • 6.9 Error and Thermal Protection

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  • 6.10 Power Sequencing

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  • 6.11 Processor Core Power Signals

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  • 6.12 Graphics and Memory Core Power Signals

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  • 6.13 Ground and NCTF

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  • 6.14 Processor Internal Pull Up/Pull Down

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• 7 Electrical Specifications

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  • 7.1 Power and Ground Lands

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  • 7.2 Decoupling Guidelines

    61
    • 7.2.1 Voltage Rail Decoupling

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  • 7.3 Processor Clocking (BCLK[0], BCLK#[0])

    62
    • 7.3.1 PLL Power Supply

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  • 7.4 VCC Voltage Identification (VID)

    62
  • 7.5 Reserved or Unused Signals

    66
  • 7.6 Signal Groups

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  • 7.7 Test Access Port (TAP) Connection

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  • 7.8 Absolute Maximum and Minimum Ratings

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  • 7.9 DC Specifications

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    • 7.9.1 Voltage and Current Specifications

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  • 7.10 Platform Environmental Control Interface (PECI) DC Specifications

    77
    • 7.10.1 DC Characteristics

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    • 7.10.2 Input Device Hysteresis

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• 8 Processor Land and Signal Information

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  • 8.1 Processor Land Assignments

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