Справочник ПользователяСодержаниеCover1Product Overview3Features4Table of Contents8List of Tables10List of Figures13Preface151 Pin and Signal Descriptions171.1 Pin Logic181.2 Pin Descriptions191.2.1 Power Supply Pins211.2.2 Miscellaneous Pin Assignment231.2.3 DDR SDRAM Interface Pin Assignments241.2.4 PCI Express Interface Pin Assignments261.2.5 SATA Interface Pin Assignments271.2.6 Gigabit Ethernet Port Interface Pin Assignments281.2.7 Serial Management Interface (SMI) Interface Pin Assignments321.2.8 USB 2.0 Interface Pin Assignments331.2.9 JTAG Interface Pin Assignment341.2.10 Real Time Clock (RTC) Interface Pin Assignments351.2.11 NAND Flash Interface Pin Assignment361.2.12 MPP Interface Pin Assignment371.2.13 Two-Wire Serial Interface (TWSI) Interface381.2.14 UART Interface391.2.15 Audio (S/PDIF / I2S) Interface401.2.16 Serial Peripheral Interface (SPI) Interface411.2.17 Secure Digital Input/Output (SDIO) Interface421.2.18 Time Division Multiplexing (TDM) Interface431.2.19 Transport Stream (TS) Interface451.2.20 Precise Timing Protocol (PTP) Interface471.3 Internal Pull-up and Pull-down Pins482 Unused Interface Strapping493 88F6281 Pin Map and Pin List504 Pin Multiplexing514.1 Multi-Purpose Pins Functional Summary514.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP574.3 TSMP (TS Multiplexing Pins) on MPP595 Clocking605.1 Spread Spectrum Clock Generator (SSCG)626 System Power Up/Down and Reset Settings636.1 Power-Up/Down Sequence Requirements636.1.1 Power-Up Sequence Requirements636.1.2 Power-Down Sequence Requirements646.2 Hardware Reset646.2.1 Reset Out Signal656.2.2 Power On Reset (POR)656.2.3 SYSRSTn Duration Counter656.3 PCI Express Reset666.3.1 PCI Express Root Complex Reset666.3.2 PCI Express Endpoint Reset666.4 Sheeva™ CPU TAP Controller Reset666.5 Pins Sample Configuration666.6 Serial ROM Initialization706.6.1 Serial ROM Data Structure706.6.2 Serial ROM Initialization Operation716.7 Boot Sequence717 JTAG Interface737.1 TAP Controller737.2 Instruction Register737.3 Bypass Register747.4 JTAG Scan Chain747.5 ID Register748 Electrical Specifications (Preliminary)758.1 Absolute Maximum Ratings758.2 Recommended Operating Conditions778.3 Thermal Power Dissipation798.4 Current Consumption808.5 DC Electrical Specifications818.5.1 General 3.3V (CMOS) DC Electrical Specifications818.5.2 RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications828.5.3 SDRAM DDR2 Interface DC Electrical Specifications838.5.4 Two-Wire Serial Interface (TWSI) 3.3V DC Electrical Specifications848.5.5 Serial Peripheral Interface (SPI) 3.3V DC Electrical Specifications848.5.6 Time Division Multiplexing (TDM) 3.3V DC Electrical Specifications858.6 AC Electrical Specifications868.6.1 Reference Clock AC Timing Specifications868.6.2 SDRAM DDR2 Interface AC Timing888.6.2.1 SDRAM DDR2 Interface AC Timing Table888.6.2.2 SDRAM DDR2 Clock Specifications908.6.2.3 SDRAM DDR2 Interface Test Circuit918.6.2.4 SDRAM DDR2 Interface AC Timing Diagrams918.6.3 Reduced Gigabit Media Independent Interface (RGMII) AC Timing938.6.3.1 RGMII AC Timing Table938.6.3.2 RGMII Test Circuit948.6.3.3 RGMII AC Timing Diagram948.6.4 Gigabit Media Independent Interface (GMII) AC Timing958.6.4.1 GMII AC Timing Table958.6.4.2 GMII Test Circuit958.6.4.3 GMII AC Timing Diagrams968.6.5 Media Independent Interface/Marvell Media Independent Interface (MII/MMII) AC Timing978.6.5.1 MII/MMII MAC Mode AC Timing Table978.6.5.2 MII/MMII MAC Mode Test Circuit978.6.5.3 MII/MMII MAC Mode AC Timing Diagrams978.6.6 Serial Management Interface (SMI) AC Timing998.6.6.1 SMI Master Mode AC Timing Table998.6.6.2 SMI Master Mode Test Circuit998.6.6.3 SMI Master Mode AC Timing Diagrams1008.6.7 JTAG Interface AC Timing1018.6.7.1 JTAG Interface AC Timing Table1018.6.7.2 JTAG Interface Test Circuit1018.6.7.3 JTAG Interface AC Timing Diagrams1028.6.8 Two-Wire Serial Interface (TWSI) AC Timing1038.6.8.1 TWSI AC Timing Table1038.6.8.2 TWSI Test Circuit1048.6.8.3 TWSI AC Timing Diagrams1048.6.9 Sony/Philips Digital Interconnect Format (S/PDIF) AC Timing1058.6.9.1 S/PDIF AC Timing Table1058.6.9.2 S/PDIF Test Circuit1068.6.10 Inter-IC Sound Interface (I2S) AC Timing1078.6.10.1 Inter-IC Sound (I2S) AC Timing Table1078.6.10.2 Inter-IC Sound (I2S) Test Circuit1078.6.10.3 Inter-IC Sound (I2S) AC Timing Diagrams1088.6.11 Time Division Multiplexing (TDM) Interface AC Timing1098.6.11.1 TDM Interface AC Timing Table1098.6.11.2 TDM Interface Test Circuit1098.6.11.3 TDM Interface Timing Diagrams1108.6.12 Serial Peripheral Interface (SPI) AC Timing1118.6.12.1 SPI (Master Mode) AC Timing Table1118.6.12.2 SPI (Master Mode) Test Circuit1118.6.12.3 SPI (Master Mode) Timing Diagrams1128.6.13 Secure Digital Input/Output (SDIO) Interface AC Timing1138.6.13.1 Secure Digital Input/Output (SDIO) AC Timing Table1138.6.13.2 Secure Digital Input/Output (SDIO) Test Circuit1138.6.13.3 Secure Digital Input/Output (SDIO) AC Timing Diagrams1148.6.14 Transport Stream (TS) Interface AC Timing1158.6.14.1 Transport Stream Interface AC Timing Table1158.6.14.2 Transport Stream Interface Test Circuit1168.6.14.3 Transport Stream Interface Timing Diagrams1168.7 Differential Interface Electrical Characteristics1188.7.1 Differential Interface Reference Clock Characteristics1188.7.1.1 PCI Express Interface Differential Reference Clock Characteristics1188.7.2 PCI Express Interface Electrical Characteristics1208.7.2.1 PCI Express Interface Driver and Receiver Characteristics1208.7.2.2 PCI Express Interface Test Circuit1218.7.3 SATA Interface Electrical Characteristics1228.7.3.1 SATA-I Interface Gen1i Mode Driver and Receiver Characteristics1238.7.3.2 SATA-II Interface Gen2i Mode Driver and Receiver Characteristics1248.7.4 USB Electrical Characteristics1258.7.4.1 USB Driver and Receiver Characteristics1258.7.4.2 USB Interface Driver Waveforms1279 Thermal Data (Preliminary)12910 Package13011 Part Order Numbering/Package Marking13211.1 Part Order Numbering13211.2 Package Marking133A Revision History134Contact Information140Размер: 1,1 МБСтраницы: 140Язык: EnglishПросмотреть