Инструкции для Maxim DS21Q55

Содержание

• FEATURE HIGHLIGHTS

  4
• General

  4
• Line Interface

  4
• Clock Synthesizer

  4
• Jitter Attenuator

  4
• Framer/Formatter

  5
• System Interface

  5
• HDLC Controllers

  6
• Test and Diagnostics

  6
• Extended System Information Bus

  6
• 1.1.10 Control Port

  6
• DOCUMENT REVISION HISTORY

  12
• BLOCK DIAGRAM

  13
• PIN FUNCTION DESCRIPTION

  14
• TRANSMIT SIDE PINS

  14
• RECEIVE SIDE PINS

  16
• PARALLEL CONTROL PORT PINS

  18
• EXTENDED SYSTEM INFORMATION BUS

  20
• JTAG TEST A CCESS PORT PINS

  20
• LINE INTERFACE PINS

  21
• SUPPLY PINS

  22
• PINOUT

  23
• PACKAGE

  29
• PARALLEL PORT

  30
• REGISTER M AP

  30
• SPECIAL PER-CHANNEL REGISTER OPERATION

  36
• PROGRAMMING MODEL

  38
• POWER-UP SEQUENCE

  39
• Master Mode Register

  39
• INTERRUPT HANDLING

  40
• STATUS REGIST ERS

  40
• INFORMATION REGISTERS

  41
• INTERRUPT INFORMATION REGISTERS

  41
• CLOCK MAP

  42
• T1 FRAMER/FORMATTER CONTROL REGISTERS

  43
• T1 CONTROL REGISTERS

  43
• T1 TRANSMIT TRANSPARENCY

  48
• T1 RECEIVE -SIDE DIGITAL-M ILLIWATT CODE GENERATION

  48
• T1 INFORMATION REGISTER

  50
• E1 FRAMER/FORMATTER CONTROL REGISTERS

  52
• E1 CONTROL REGISTERS

  52
• A UTOMATIC A LARM GENERATION

  56
• E1 INFORMATION REGISTERS

  57
• COMMON CONTROL AND STATUS REGISTERS

  59
• I/O PIN CONFIGURATION OPTIONS

  66
• LOOPBACK CONFIGURATION

  68
• PER-CHANNEL LOOPBACK

  70
• ERROR COUNT REGISTERS

  72
• LINE CODE VIOLATION COUNT REGISTER (LCVCR)

  73
• PATH CODE VIOLATION COUNT REGISTER (PCVCR)

  75
• FRAMES OUT OF SYNC COUNT REGISTER (FOSCR)

  76
• E-BIT COUNTER REGISTER (EBCR)

  78
• DS0 MONITORING FUNCTION

  79
• TRANSMIT DS0 M ONITOR REGISTERS

  79
• RECEIVE DS0 M ONITOR REGISTERS

  80
• SIGNALING OPERATION

  81
• 15.1 RECEIVE SIGNALING

  81
• 15.1.1 Processor-Based Receive Signaling

  82
• 15.1.2 Hardware-Based Receive Signaling

  82
• 15.2 TRANSMIT SIGNALING

  87
• 15.2.1 Processor-Based Transmit Signaling

  87
• 15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode

  93
• 15.2.3 Software Signaling Insertion Enable Registers, T1 Mode

  95
• PER-CHANNEL IDLE CODE GENERATION

  97
• IDLE CODE PROGRAMMING EXAMPLES

  98
• CHANNEL BLOCKING REGISTERS

  103
• ELASTIC STORES OPERATION

  106
• 18.1 RECEIVE SIDE

  110
• 18.1.1 T1 Mode

  110
• 18.1.2 E1 Mode

  110
• 18.2 TRANSMIT SIDE

  111
• 18.2.1 T1 Mode

  111
• 18.2.2 E1 Mode

  111
• 18.3 ELASTIC STORES INITIALIZATION

  111
• 18.4 M INIMUM -DELAY M ODE

  111
• G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)

  113
• T1 BIT ORIENTED CODE (BOC) CONTROLLER

  114
• TRANSMIT BOC

  114
• RECEIVE BOC

  114
• ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)

  118
• HARDWARE SCHEME (M ETHOD 1)

  118
• INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (M ETHOD 2)

  118
• INTERNAL REGISTER SCHEME BASED ON CRC4 M ULTIFRAME (M ETHOD 3)

  121
• HDLC CONTROLLERS

  132
• 22.1 BASIC OPERATION DETAILS

  132
• 22.2 HDLC CONFIGURATION

  134
• 22.2.1 FIFO Control

  136
• 22.3 HDLC M APPING

  137
• 22.3.1 Receive

  137
• 22.3.2 Transmit

  139
• 22.3.3 FIFO Information

  144
• 22.3.4 Receive Packet Bytes Available

  144
• 22.3.5 HDLC FIFOS

  145
• 22.4 RECEIVE HDLC CODE EXAMPLE

  146
• 22.5 LEGACY FDL SUPPORT (T1 M ODE)

  146
• 22.5.1 Receive Section

  146
• 22.5.2 Transmit Section

  148
• 22.6 D4/SLC– 96 OPERATION

  148
• LINE INTERFACE UNIT (LIU)

  149
• 23.1 LIU OPERATION

  150
• 23.2 LIU RECEIVER

  150
• 23.2.2 Receive G.703 Synchronization Signal (E1 Mode)

  151
• 23.2.3 Monitor Mode

  151
• 23.3 LIU TRANSMITTER

  152
• 23.3.1 Transmit Short-Circuit Detector/Limiter

  152
• 23.3.2 Transmit Open-Circuit Detector

  152
• 23.3.3 Transmit BPV Error Insertion

  152
• 23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)

  152
• 23.4 MCLK PRESCALER

  153
• 23.5 JITTER ATTENUATOR

  153
• 23.6 CMI (CODE M ARK INVERSION) OPTION

  153
• 23.7 LIU CONTROL REGISTERS

  154
• 23.8 RECOMMENDED CIRCUITS

  164
• 23.9 COMPONENT SPECIFICATIONS

  166
• PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION

  170
• BERT FUNCTION

  177
• BERT REGISTER DESCRIPTION

  178
• BERT REPETITIVE PATTERN SET

  183
• BERT BIT COUNTER

  184
• BERT ERROR COUNTER

  185
• PAYLOAD ERROR INSERTION FUNCTION

  186
• 26.1 NUMBER OF ERROR REGISTERS

  188
• 26.1.1 Number Of Errors Left Register

  189
• INTERLEAVED PCM BUS OPERATION

  190
• CHANNEL INTERLEAVE M ODE

  190
• FRAME INTERLEAVE MODE

  190
• EXTENDED SYSTEM INFORMATION BUS (ESIB)

  193
• PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER

  197
• FRACTIONAL T1/E1 SUPPORT

  198
• JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT

  199
• INSTRUCTION REGISTER

  203
• TEST REGISTERS

  205
• BOUNDARY SCAN REGISTER

  205
• BYPASS REGISTER

  205
• IDENTIFICATION REGISTER

  205
• FUNCTIONAL TIMING DI AGRAMS

  208
• T1 M ODE

  208
• 32.2 E1 M ODE

  218
• OPERATING PARAMETERS

  231
• AC TIMING PARAMETERS AND DIAGRAMS

  233
• M ULTIPEXED BUS AC CHARACTERISTICS

  233
• NONMULTIPLEXED BUS AC CHARACTERISTICS

  236
• RECEIVE SIDE AC CHARACTERISTICS

  239
• TRANSMIT AC CHARACTERISTICS

  243
• MECHANICAL DESCRIPTIONS

  247