Техническая СпецификацияСодержаниеTABLE 1: Silicon DEVREV Values1TABLE 2: Silicon Issue Summary2Silicon Errata Issues31. Module: Master Synchronous Serial Port (MSSPx)32. Module: Oscillator Configurations (PLL)33. Module: Voltage Regulator34. Module: SRAM4TABLE 3: Typical Current Consumption45. Module: Low-Voltage Detect46. Module: MSSPx (I2C™ Master)47. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)4Data Sheet Clarifications51. Module: Table 27-1: Memory Programming Requirements5TABLE 27-1: Memory Programming Requirements52. Module: Table 27-2: Comparator Specifications6TABLE 27-2: Comparator Specifications63. Module: Table 27-4: Internal Voltage Regulator Specifications6TABLE 27-4: Internal Voltage Regulator Specifications64. Module: Section 27.3 “DC Characteristics: PIC18F87J11 Family (Industrial)”75. Module: Example 6-2: Erasing a Flash Program Memory Row8EXAMPLE 6-2: Erasing a Flash Program Memory Row86. Module: Section 19.3 “SPI Mode” and Section 19.4 “I2C™ Mode”87. Module: Figure 19-10: I2C™ Slave Mode Timing (Transmission, 7-Bit Address)8FIGURE 19-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)98. Module: Figure 19-24: I2C™ Master Mode Waveform (Reception, 7-Bit Address)10FIGURE 19-24: I2C™ Master Mode Waveform (RECEPTION, 7-BIT ADDRESS)119. Module: Table 1-3: PIC18F6XJ1X Pinout I/O Descriptions1210. Module: Memory Organization1311. Module: Memory Organization13FIGURE 5-7: Data Memory Map for PIC18F87J11 family Devices1412. Module: Electrical Specification1527.1 DC Characteristics: Supply Voltage PIC18F87J11 Family (Industrial)15Document Revision History16Worldwide Sales and Service18Размер: 141,1 КБСтраницы: 18Язык: EnglishПросмотреть
Справочник ПользователяСодержаниеChapter 1. Introduction91.1 Introduction91.2 Development Kit Contents91.3 PICDEM™ PIC18 Explorer Demonstration Board10Figure 1-1: PICDEM™ PIC18 Explorer Demonstration Board111.4 Sample Devices111.5 Sample Programs11Chapter 2. Getting Started13Table 2-1: PICDEM™ PIC18 Explorer Demonstration Board Configurations132.1 Board as Stand-Alone Device132.1.1 Using the Board As Is14Figure 2-1: S4 Switch – Setting for Default Main Microcontroller14Figure 2-2: JP1, JP2 and JP3 Jumpers142.1.2 Reprogramming the Microcontroller152.2 Board with In-Circuit Debugger15Figure 2-3: Board with MPLAB® ICD 2 In-Circuit Debugger Attached152.3 Board with PIM Attached Devices16Figure 2-4: PICDEM™ PIC18 Explorer Demonstration Board with PIM162.3.1 Attaching the PIM17Figure 2-5: PIM Connectors and S4 Switch17Figure 2-6: S4 Switch – Setting for PIM-Mounted Devices172.3.2 Varying the Device Voltage (5V/3.3V)182.3.3 Calculating Other Vdd Values19Equation 2-1: Regulator Voltage Output19Equation 2-2: Calculating Output Voltage19Table 2-2: Calculating R101, R102 Values for Vdd Outputs†192.4 Programming the Microcontrollers202.4.1 Programming Requirements202.4.2 Loading the Program212.4.2.1 Reprogramming with the Compact Disc Sample Code21Figure 2-7: J4 Jumper And ‘main’ Setting21Figure 2-8: J4 Jumper and ‘USB’ Setting222.5 Connecting to Host PC for RS-232 Communication23Figure 2-9: Board to PC Connection232.5.1 PC Connection Via DB9 Pin23Figure 2-10: Jumper J13 – Settings for RS-232 or USB232.5.2 PC Connection Via USB Port24Figure 2-11: Installing USB *.inf File on PC – Screen 124Figure 2-12: Installing USB *.inf File on PC – Screen 225Figure 2-13: Installing USB *.inf File on Pc – Screen 425Chapter 3. PICDEM™ PIC18 Explorer Demonstration Board Tutorial Program273.1 Tutorial Program Operation27Figure 3-1: RB0 and RA5 Buttons27Table 3-1: Hyper Terminal Settings28Figure 3-2: Tutorial Program Flowchart293.2 Source Code and Data Sheets29Appendix A. Hardware Details31A.1 Hardware Elements31A.1.1 Processor Sockets31A.1.2 Display31A.1.3 Power Supply31A.1.4 RS-232 Serial Port31A.1.5 Switches32A.1.6 Oscillator Options32A.1.7 Analog Input (Potentiometer)32A.1.8 ICD Connector32A.1.9 PICkit™ 2 Connector32A.1.10 Temperature Sensor32A.1.11 Serial EEPROM32A.1.12 PICtail™ Daughter Board Connector32A.1.13 LCD33A.1.14 Sample Devices33Table A-1: Sample Device I/O Features and Connections33A.2 Board Layout and Schematics34Figure A-1: PICDEM™ PIC18 Explorer Demonstration Board Layout34Figure A-2: PICDEM™ PIC18 Explorer Demonstration Board Schematic – 1 of 235Figure A-3: PICDEM™ PIC18 Explorer Demonstration Board Schematic – 2 of 236Worldwide Sales and Service38Размер: 1,2 МБСтраницы: 38Язык: EnglishПросмотреть
Техническая СпецификацияСодержание1. Module: Master Synchronous Serial Port (MSSP)1Revision History2Worldwide Sales and Service4Размер: 70,3 КБСтраницы: 4Язык: EnglishПросмотреть
Техническая СпецификацияСодержание1. Module: Master Synchronous Serial Port (MSSP) — Serial Peripheral Interface (SPI)12. Module: Capture/Compare/PWM (CCP)13. Module: MSSP (I2C™ Slave)14. Module: MSSP (I2C™ Master)25. Module: Enhanced Universal Synchronous Asynchronous (EUSART)26. Module: Timer12Revision History3Размер: 86,1 КБСтраницы: 6Язык: EnglishПросмотреть
Техническая СпецификацияСодержаниеPower Management Features:3Flexible Oscillator Structure:3Peripheral Highlights:3Peripheral Highlights (Continued):3Special Microcontroller Features:3Pin Diagrams4Table of Contents6Most Current Data Sheet7Errata7Customer Notification System71.0 Device Overview91.1 New Core Features91.1.1 nanoWatt Technology91.1.2 Expanded Memory91.1.3 Multiple Oscillator Options and Features91.1.4 External Memory Interface101.1.5 Easy Migration101.2 Other Special Features101.3 Details on Individual Family Members11TABLE 1-1: Device Features (PIC18F6527/6622/6627/6722)11TABLE 1-2: Device Features (PIC18F8527/8622/8627/8722)12FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-pin) Block Diagram13FIGURE 1-2: PIC18F8527/8622/8627/8722 (80-pin) Block Diagram14TABLE 1-3: PIC18F6527/6622/6627/6722 Pinout I/O Descriptions15TABLE 1-4: PIC18F8527/8622/8627/8722 Pinout I/O Descriptions232.0 Oscillator Configurations332.1 Oscillator Types332.2 Crystal Oscillator/Ceramic Resonators33FIGURE 2-1: Crystal/Ceramic Resonator Operation (XT, LP, HS or HSPLL Configuration)33TABLE 2-1: Capacitor Selection for Ceramic Resonators33TABLE 2-2: Capacitor Selection for Quartz Crystals34FIGURE 2-2: External Clock Input Operation (HS Osc Configuration)342.3 External Clock Input34FIGURE 2-3: External Clock Input Operation (EC Configuration)34FIGURE 2-4: External Clock Input Operation (ECIO Configuration)342.4 RC Oscillator35FIGURE 2-5: RC Oscillator Mode35FIGURE 2-6: RCIO Oscillator Mode352.5 PLL Frequency Multiplier352.5.1 HSPLL Oscillator Mode35FIGURE 2-7: HSPLL Block Diagram352.5.2 PLL and INTOSC352.6 Internal Oscillator Block362.6.1 INTIO Modes36FIGURE 2-8: INTIO1 Oscillator Mode36FIGURE 2-9: INTIO2 Oscillator Mode362.6.2 INTOSC Output Frequency362.6.3 OSCTUNE Register36FIGURE 2-10: INTOSC and PLL Block Diagram362.6.4 PLL in INTOSC Modes372.6.5 INTOSC Frequency Drift37Register 2-1: OSCTUNE: Oscillator Tuning Register372.7 Clock Sources and Oscillator Switching39FIGURE 2-11: PIC18F8722 Family Clock Diagram392.7.1 Oscillator Control Register402.7.2 Oscillator Transitions40Register 2-2: OSCCON: Oscillator Control Register412.8 Effects of Power-Managed Modes on the Various Clock Sources422.9 Power-up Delays422.9.1 Delays for Power-up and Return to Primary Clock42TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode423.0 Power-Managed Modes433.1 Selecting Power-Managed Modes433.1.1 Clock Sources433.1.2 Entering Power-Managed Modes43TABLE 3-1: Power-Managed Modes433.1.3 Clock Transitions and Status Indicators443.1.4 Multiple Sleep Commands443.2 Run Modes443.2.1 PRI_RUN Mode443.2.2 SEC_RUN Mode44FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode45FIGURE 3-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)453.2.3 RC_RUN Mode45FIGURE 3-3: Transition Timing to RC_RUN Mode46FIGURE 3-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode463.3 Sleep Mode473.4 Idle Modes47FIGURE 3-5: Transition Timing for Entry to Sleep Mode47FIGURE 3-6: Transition Timing for Wake From Sleep (HSPLL)473.4.1 PRI_IDLE Mode483.4.2 SEC_IDLE Mode48FIGURE 3-7: Transition Timing for Entry to Idle Mode48FIGURE 3-8: Transition Timing for Wake From Idle to Run Mode483.4.3 RC_IDLE Mode493.5 Exiting Idle and Sleep Modes493.5.1 Exit By Interrupt493.5.2 Exit By WDT Time-out493.5.3 Exit By Reset493.5.4 Exit Without an Oscillator Start-up Delay50TABLE 3-2: Exit Delay on Wake-up By Reset From Sleep Mode or Any Idle Mode (By Clock Sources)504.0 Reset514.1 RCON Register51FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit51Register 4-1: RCON: Reset Control Register524.2 Master Clear (MCLR)534.3 Power-on Reset (POR)53FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)(1)534.4 Brown-out Reset (BOR)544.4.1 Software Enabled BOR544.4.2 Detecting BOR544.4.3 Disabling BOR in Sleep Mode54TABLE 4-1: BOR Configurations544.5 Device Reset Timers554.5.1 Power-up Timer (PWRT)554.5.2 Oscillator Start-up Timer (OST)554.5.3 PLL Lock Time-out554.5.4 Time-out Sequence55TABLE 4-2: Time-out in Various Situations55FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)56FIGURE 4-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 156FIGURE 4-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 256FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)57FIGURE 4-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)574.6 Reset State of Registers58TABLE 4-3: Status Bits, Their Significance and The Initialization Condition for RCON Register58TABLE 4-4: Initialization Conditions for All Registers595.0 Memory Organization655.1 Program Memory Organization655.1.1 PIC18F8527/8622/8627/8722 Program Memory Modes65FIGURE 5-1: Program Memory Map and Stack for PIC18F8722 Family Devices66TABLE 5-1: Memory Access for PIC18F8527/8622/8627/8722 Program Memory Modes66FIGURE 5-2: Memory Maps for PIC18F8722 Family Program Memory Modes675.1.2 Program Counter685.1.3 Return Address Stack68FIGURE 5-3: Return Address Stack and Associated Registers68Register 5-1: STKPTR: Stack Pointer Register695.1.4 Fast Register Stack70EXAMPLE 5-1: Fast Register Stack Code Example705.1.5 Look-up Tables in Program Memory70EXAMPLE 5-2: Computed GOTO Using an Offset Value705.2 PIC18 Instruction Cycle715.2.1 Clocking Scheme715.2.2 Instruction Flow/Pipelining71FIGURE 5-4: Clock/ Instruction Cycle71EXAMPLE 5-3: Instruction Pipeline Flow715.2.3 Instructions in Program Memory72FIGURE 5-5: Instructions in Program Memory725.2.4 Two-Word Instructions73EXAMPLE 5-4: Two-Word Instructions735.3 Data Memory Organization745.3.1 Bank Select Register (BSR)74FIGURE 5-6: Data Memory Map for the PIC18F8722 Family of Devices75FIGURE 5-7: Use of the Bank Select Register (Direct Addressing)765.3.2 Access Bank765.3.3 General Purpose Register File765.3.4 Special Function Registers77TABLE 5-2: Special Function Register Map for the PIC18F8722 Family of Devices77TABLE 5-3: Register File Summary785.3.5 STATUS Register82Register 5-2: STATUS: Arithmetic Status Register825.4 Data Addressing Modes835.4.1 Inherent and Literal Addressing835.4.2 Direct Addressing835.4.3 Indirect Addressing83EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing83FIGURE 5-8: Indirect Addressing845.5 Data Memory and the Extended Instruction Set855.5.1 Indexed Addressing with Literal Offset855.5.2 Instructions Affected By Indexed Literal Offset Mode85FIGURE 5-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)865.5.3 Mapping the Access Bank in Indexed Literal Offset Mode875.6 PIC18 Instruction Execution and the Extended Instruction Set87FIGURE 5-10: Remapping the Access Bank with Indexed Literal Offset Addressing876.0 Flash Program Memory896.1 Table Reads and Table Writes89FIGURE 6-1: Table Read Operation89FIGURE 6-2: Table Write Operation906.2 Control Registers906.2.1 EECON1 and EECON2 Registers90Register 6-1: EECON1: EEPROM Control Register 1916.2.2 TABLAT – Table Latch Register926.2.3 TBLPTR – Table Pointer Register926.2.4 Table Pointer Boundaries92TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions92FIGURE 6-3: Table Pointer Boundaries Based on Operation926.3 Reading the Flash Program Memory93FIGURE 6-4: Reads From Flash Program Memory93EXAMPLE 6-1: Reading a Flash Program Memory Word936.4 Erasing Flash Program Memory946.4.1 Flash Program Memory Erase Sequence94EXAMPLE 6-2: Erasing a Flash Program Memory Row946.5 Writing to Flash Program Memory95FIGURE 6-5: Table Writes to Flash Program Memory956.5.1 Flash Program Memory Write Sequence95EXAMPLE 6-3: Writing to Flash Program Memory96EXAMPLE 6-3: Writing to Flash Program Memory (Continued)976.5.2 Write Verify976.5.3 Unexpected Termination of Write Operation976.5.4 Protection Against Spurious Writes976.6 Flash Program Operation During Code Protection97TABLE 6-2: Registers Associated with Program Flash Memory977.0 External Memory Bus99TABLE 7-1: PIC18F8527/8622/8627/8722 External Bus – I/O Port Functions997.1 External Memory Bus Control100Register 7-1: MEMCON: External Memory Bus Control Register1007.2 Address and Data Width1017.2.1 21-Bit Addressing1017.3 Wait States101TABLE 7-2: Address and Data Lines for Different Address and Data Widths1017.4 Program Memory Modes and the External Memory Bus1027.5 16-Bit Data Width Modes1027.5.1 16-Bit Byte Write Mode103FIGURE 7-1: 16-Bit Byte Write Mode Example1037.5.2 16-Bit Word Write Mode104FIGURE 7-2: 16-Bit Word Write Mode Example1047.5.3 16-bit Byte Select Mode105FIGURE 7-3: 16-Bit Byte Select Mode Example1057.5.4 16-Bit Mode Timing106FIGURE 7-4: External Memory Bus Timing for TBLRD with a 1 Tcy Wait State (Microprocessor Mode)106FIGURE 7-5: External Memory Bus Timing for TBLRD (Extended Microcontroller Mode)106FIGURE 7-6: External Memory Bus Timing for SLEEP (Microprocessor Mode)1077.6 8-Bit Data Width Modes108FIGURE 7-7: 8-Bit Multiplexed Mode Example1087.6.1 8-Bit Mode Timing109FIGURE 7-8: External Bus Timing for TBLRD (Microprocessor Mode)109FIGURE 7-9: External Bus Timing for TBLRD (Extended Microcontroller Mode)109FIGURE 7-10: External Memory Bus Timing for SLEEP (Microprocessor Mode)110FIGURE 7-11: Typical Opcode Fetch, 8-Bit Mode1107.7 Operation in Power-Managed Modes111TABLE 7-3: Summary of Registers Associated with Power-Managed Modes1118.0 Data EEPROM Memory1138.1 EEADR and EEADRH Registers1138.2 EECON1 and EECON2 Registers113Register 8-1: EECON1: Data EEPROM Control Register 11148.3 Reading the Data EEPROM Memory1158.4 Writing to the Data EEPROM Memory1158.5 Write Verify115EXAMPLE 8-1: Data EEPROM Read115EXAMPLE 8-2: Data EEPROM Write1158.6 Operation During Code-Protect1168.7 Protection Against Spurious Write1168.8 Using the Data EEPROM116EXAMPLE 8-3: Data EEPROM Refresh Routine116TABLE 8-1: Registers Associated with Data EEPROM Memory1179.0 8 X 8 Hardware Multiplier1199.1 Introduction1199.2 Operation119EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine119EXAMPLE 9-2: 8 x 8 Signed Multiply Routine119TABLE 9-1: Performance Comparison for Various Multiply Operations119EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm120EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine120EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm120EXAMPLE 9-4: 16 x 16 Signed Multiply Routine12010.0 Interrupts121FIGURE 10-1: PIC18F8722 Family Interrupt Logic12210.1 INTCON Registers123Register 10-1: INTCON: Interrupt Control Register123Register 10-2: INTCON2: Interrupt Control Register 2124Register 10-3: INTCON3: Interrupt Control Register 312510.2 PIR Registers126Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1126Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2127Register 10-6: PIR3: Peripheral Interrupt Request (Flag) Register 312810.3 PIE Registers129Register 10-7: PIE1: Peripheral Interrupt Enable Register 1129Register 10-8: PIE2: Peripheral Interrupt Enable Register 2130Register 10-9: PIE3: Peripheral Interrupt Enable Register 313110.4 IPR Registers132Register 10-10: IPR1: Peripheral Interrupt Priority Register 1132Register 10-11: IPR2: Peripheral Interrupt Priority Register 2133Register 10-12: IPR3: Peripheral Interrupt Priority Register 313410.5 RCON Register135Register 10-13: RCON: Reset Control Register13510.6 INTx Pin Interrupts13610.7 TMR0 Interrupt13610.8 PORTB Interrupt-on-Change13610.9 Context Saving During Interrupts136EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM13611.0 I/O Ports137FIGURE 11-1: Generic I/O Port Operation13711.1 PORTA, TRISA and LATA Registers137EXAMPLE 11-1: Initializing PORTA137TABLE 11-1: PORTA Functions138TABLE 11-2: Summary of Registers Associated with PORTA13811.2 PORTB, TRISB and LATB Registers139EXAMPLE 11-2: Initializing PORTB139TABLE 11-3: PORTB Functions140TABLE 11-4: Summary of Registers Associated with Portb14111.3 PORTC, TRISC and LATC Registers142EXAMPLE 11-3: Initializing PORTC142TABLE 11-5: PORTC Functions143TABLE 11-6: Summary of Registers Associated with PORTC14411.4 PORTD, TRISD and LATD Registers145EXAMPLE 11-4: Initializing PORTD145TABLE 11-7: PORTD Functions146TABLE 11-8: Summary of Registers Associated with Portd14711.5 PORTE, TRISE and LATE Registers148EXAMPLE 11-5: Initializing PORTE148TABLE 11-9: PORTE Functions149TABLE 11-10: Summary of Registers Associated with PORTE15011.6 PORTF, LATF and TRISF Registers151EXAMPLE 11-6: Initializing PORTF151TABLE 11-11: PORTF Functions152TABLE 11-12: Summary of Registers Associated with PORTF15211.7 PORTG, TRISG and LATG Registers153EXAMPLE 11-7: Initializing PORTG153TABLE 11-13: PORTG Functions154TABLE 11-14: Summary of Registers Associated with PORTG15511.8 PORTH, LATH and TRISH Registers156EXAMPLE 11-8: Initializing PORTH156TABLE 11-15: PORTH Functions157TABLE 11-16: Summary of Registers Associated with PORTH15711.9 PORTJ, TRISJ and LATJ Registers158EXAMPLE 11-9: Initializing PORTJ158TABLE 11-17: PORTJ Functions159TABLE 11-18: Summary of Registers Associated with PORTJ15911.10 Parallel Slave Port160FIGURE 11-2: PORTD and PORTE Block Diagram (Parallel Slave Port)160Register 11-1: PSPCON: Parallel Slave Port Control Register161FIGURE 11-3: Parallel Slave Port Write Waveforms162FIGURE 11-4: Parallel Slave Port Read Waveforms162TABLE 11-19: Registers Associated with Parallel Slave Port16212.0 Timer0 Module163Register 12-1: T0CON: Timer0 Control Register16312.1 Timer0 Operation16412.2 Timer0 Reads and Writes in 16-bit Mode164FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)164FIGURE 12-2: Timer0 Block Diagram (16-Bit Mode)16412.3 Prescaler16512.3.1 Switching Prescaler Assignment16512.4 Timer0 Interrupt165TABLE 12-1: Registers Associated with Timer016513.0 Timer1 Module167Register 13-1: T1CON: Timer1 Control Register16713.1 Timer1 Operation168FIGURE 13-1: Timer1 Block Diagram168FIGURE 13-2: Timer1 Block Diagram (16-Bit Read/Write Mode)16813.2 Timer1 16-bit Read/Write Mode16913.3 Timer1 Oscillator169FIGURE 13-3: External Components for the Timer1 LP Oscillator169TABLE 13-1: Capacitor Selection for the Timer Oscillator(2,3,4)16913.3.1 Using Timer1 as a Clock Source16913.3.2 Low-Power Timer1 Option16913.3.3 Timer1 Oscillator Layout Considerations17013.4 Timer1 Interrupt17013.5 Resetting Timer1 Using the CCP Special Event Trigger17013.6 Using Timer1 as a Real-Time Clock170EXAMPLE 13-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service171TABLE 13-2: Registers Associated with Timer1 as a Timer/Counter17114.0 Timer2 Module17314.1 Timer2 Operation173Register 14-1: T2CON: Timer2 Control Register17314.2 Timer2 Interrupt17414.3 Timer2 Output174FIGURE 14-1: Timer2 Block Diagram174TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter17415.0 Timer3 Module175Register 15-1: T3CON: Timer3 Control Register17515.1 Timer3 Operation176FIGURE 15-1: Timer3 Block Diagram176FIGURE 15-2: Timer3 Block Diagram (16-Bit Read/Write Mode)17615.2 Timer3 16-bit Read/Write Mode17715.3 Using the Timer1 Oscillator as the Timer3 Clock Source17715.4 Timer3 Interrupt17715.5 Resetting Timer3 Using the CCP Special Event Trigger177TABLE 15-1: Registers Associated with Timer3 as a Timer/Counter17716.0 Timer4 Module17916.1 Timer4 Operation179Register 16-1: T4CON: Timer4 Control Register17916.2 Timer4 Interrupt18016.3 Output of TMR4180FIGURE 16-1: Timer4 Block Diagram180TABLE 16-1: Registers Associated with Timer4 as a Timer/Counter18017.0 Capture/Compare/PWM (CCP) Modules181Register 17-1: CCPxCON: CCPx Control Register (CCP4 and CCP5 Modules)18117.1 CCP Module Configuration18217.1.1 CCP Modules and Timer Resources182TABLE 17-1: CCP Mode – Timer Resource18217.1.2 ECCP2 Pin Assignment182FIGURE 17-1: CCP and Timer Interconnect Configurations18217.2 Capture Mode18317.2.1 CCPx Pin Configuration18317.2.2 Timer1/Timer3 Mode Selection18317.2.3 Software Interrupt18317.2.4 CCP Prescaler183EXAMPLE 17-1: Changing Between Capture Prescalers (CCP5 Shown)183FIGURE 17-2: Capture Mode Operation Block Diagram18317.3 Compare Mode18417.3.1 CCPx Pin Configuration18417.3.2 Timer1/Timer3 Mode Selection18417.3.3 Software Interrupt Mode18417.3.4 Special Event Trigger184FIGURE 17-3: Compare Mode Operation Block Diagram184TABLE 17-2: Registers Associated with Capture, Compare, Timer1 and Timer318517.4 PWM Mode186FIGURE 17-4: Simplified PWM Block Diagram186FIGURE 17-5: PWM Output18617.4.1 PWM Period186EQUATION 17-1:18617.4.2 PWM Duty Cycle186EQUATION 17-2:186EQUATION 17-3:18717.4.3 Setup for PWM Operation187TABLE 17-3: Example PWM Frequencies and Resolutions at 40 MHz187TABLE 17-4: Registers Associated with PWM, Timer2 and Timer418818.0 Enhanced Capture/ Compare/PWM (ECCP) Module189Register 18-1: CCPxCON: Enhanced CCPx Control Register (ECCP1, ECCP2, ECCP3)18918.1 ECCP Outputs and Configuration19018.1.1 Use of CCP4 and CCP5 with ECCP1 and ECCP319018.1.2 ECCP Module Outputs, Program Memory Modes and EMB Address Bus Width190TABLE 18-1: Pin Configurations for ECCP1191TABLE 18-2: Pin Configurations for ECCP2192TABLE 18-3: Pin Configurations for ECCP319318.1.3 ECCP Modules and Timer Resources19418.2 Capture and Compare Modes19418.2.1 Special Event Trigger19418.3 Standard PWM Mode19418.4 Enhanced PWM Mode19418.4.1 PWM Period194EQUATION 18-1:194FIGURE 18-1: Simplified Block Diagram of the Enhanced PWM Module19518.4.2 PWM Duty Cycle195EQUATION 18-2:195EQUATION 18-3:195TABLE 18-4: Example PWM Frequencies and Resolutions at 40 MHz19518.4.3 PWM Output Configurations196FIGURE 18-2: PWM Output Relationships (Active-High State)196FIGURE 18-3: PWM Output Relationships (Active-Low State)19718.4.4 Half-Bridge Mode198FIGURE 18-4: Half-Bridge PWM Output198FIGURE 18-5: Examples of Half-Bridge Output Mode Applications19818.4.5 Full-Bridge Mode199FIGURE 18-6: Full-Bridge PWM Output199FIGURE 18-7: Example of Full-Bridge Application200FIGURE 18-8: PWM Direction Change201FIGURE 18-9: PWM Direction Change at Near 100% Duty Cycle(1)20118.4.6 Programmable Dead-Band Delay20218.4.7 Enhanced PWM Auto-Shutdown202Register 18-2: ECCPxDEL: Enhanced PWM Dead-Band Delay Register202Register 18-3: ECCPxAS: Enhanced CCP Auto-Shutdown Configuration Register20318.4.8 Start-up Considerations204FIGURE 18-10: PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled)204FIGURE 18-11: PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Disabled)20418.4.9 Setup for PWM Operation20518.4.10 Operation in Power-Managed Modes20518.4.11 Effects of a Reset205TABLE 18-5: Registers Associated with ECCP Modules and Timer1 to Timer420619.0 Master Synchronous Serial Port (MSSP) Module20719.1 Master SSP (MSSP) Module Overview20719.2 Control Registers20719.3 SPI Mode207FIGURE 19-1: MSSP Block Diagram (SPI Mode)20719.3.1 Registers208Register 19-1: SSPxSTAT: MSSPx Status Register (SPI Mode)208Register 19-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)20919.3.2 Operation210EXAMPLE 19-1: Loading the SSP1BUF (SSP1SR) Register21019.3.3 Enabling SPI I/O21119.3.4 Typical Connection211FIGURE 19-2: SPI Master/Slave Connection21119.3.5 Master Mode212FIGURE 19-3: SPI Mode Waveform (Master Mode)21219.3.6 Slave Mode21319.3.7 Slave Select Synchronization213FIGURE 19-4: Slave Synchronization Waveform213FIGURE 19-5: SPI Mode Waveform (Slave Mode with CKE = 0)214FIGURE 19-6: SPI Mode Waveform (Slave Mode with CKE = 1)21419.3.8 Operation in Power-Managed Modes21519.3.9 Effects of a Reset21519.3.10 Bus Mode Compatibility215TABLE 19-1: SPI Bus Modes21519.3.11 SPI Clock Speed and Module Interactions215TABLE 19-2: Registers Associated with SPI Operation21619.4 I2C Mode217FIGURE 19-7: MSSP Block Diagram (I2C™ Mode)21719.4.1 RegistersRegister 19-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)218Register 19-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)219Register 19-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Mode)22019.4.2 Operation22119.4.3 Slave Mode221FIGURE 19-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)223FIGURE 19-9: I2C™ Slave Mode Timing (Transmission, 7-bit Address)224FIGURE 19-10: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)225FIGURE 19-11: I2C™ Slave Mode Timing (Transmission, 10-bit Address)22619.4.4 Clock Stretching227FIGURE 19-12: Clock Synchronization Timing228FIGURE 19-13: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)229FIGURE 19-14: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)23019.4.5 General Call Address Support231FIGURE 19-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode)23119.4.6 Master Mode232FIGURE 19-16: MSSP Block Diagram (I2C™ Master Mode)23219.4.7 Baud Rate234FIGURE 19-17: Baud Rate Generator Block Diagram234TABLE 19-3: I2C™ Clock Rate w/BRG234FIGURE 19-18: Baud Rate Generator Timing with Clock Arbitration23519.4.8 I2C Master Mode Start Condition Timing236FIGURE 19-19: First Start Bit Timing23619.4.9 I2C Master Mode Repeated Start Condition Timing237FIGURE 19-20: Repeated Start Condition Waveform23719.4.10 I2C Master Mode Transmission23819.4.11 I2C Master Mode Reception238FIGURE 19-21: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)239FIGURE 19-22: I2C™ Master Mode Waveform (Reception, 7-bit Address)24019.4.12 Acknowledge Sequence Timing24119.4.13 Stop Condition Timing241FIGURE 19-23: Acknowledge Sequence Waveform241FIGURE 19-24: Stop Condition Receive or Transmit Mode24119.4.14 Sleep Operation24219.4.15 Effects of a Reset24219.4.16 Multi-Master Mode24219.4.17 Multi -master Communication, Bus Collision and Bus Arbitration242FIGURE 19-25: Bus Collision Timing for Transmit and Acknowledge242FIGURE 19-26: Bus Collision During Start Condition (SDAx Only)243FIGURE 19-27: Bus Collision During Start Condition (SCLx = 0)244FIGURE 19-28: BRG Reset Due to SDAx Arbitration During Start Condition244FIGURE 19-29: Bus Collision During a Repeated Start Condition (Case 1)245FIGURE 19-30: Bus Collision During Repeated Start Condition (Case 2)245FIGURE 19-31: Bus Collision During a Stop Condition (Case 1)246FIGURE 19-32: Bus Collision During a Stop Condition (Case 2)246TABLE 19-4: Registers Associated with I2C™ Operation24720.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)249Register 20-1: TXSTAx: Transmit Status and Control Register250Register 20-2: RCSTAx: Receive Status and Control Register251Register 20-3: BAUDCONx: Baud Rate Control Register25220.1 Baud Rate Generator (BRG)25320.1.1 Operation in Power-Managed Modes25320.1.2 Sampling253TABLE 20-1: Baud Rate Formulas253EXAMPLE 20-1: Calculating Baud Rate Error254TABLE 20-2: Registers Associated with Baud Rate Generator254TABLE 20-3: Baud Rates for Asynchronous Modes25520.1.3 Auto-Baud Rate Detect257TABLE 20-4: BRG Counter Clock Rates257FIGURE 20-1: Automatic Baud Rate Calculation258FIGURE 20-2: BRG Overflow Sequence25820.2 EUSART Asynchronous Mode25920.2.1 EUSART Asynchronous Transmitter259FIGURE 20-3: EUSART Transmit Block Diagram260FIGURE 20-4: Asynchronous Transmission260FIGURE 20-5: Asynchronous Transmission (Back to Back)260TABLE 20-5: Registers Associated with Asynchronous Transmission26120.2.2 EUSART Asynchronous Receiver26220.2.3 Setting Up 9-bit Mode with Address Detect262FIGURE 20-6: EUSART Receive Block Diagram262FIGURE 20-7: Asynchronous Reception263TABLE 20-6: Registers Associated with Asynchronous Reception26320.2.4 Auto-Wake-up on Sync Break Character264FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation264FIGURE 20-9: Auto-Wake-up Bit (WUE) Timings During Sleep26420.2.5 Break Character Sequence26520.2.6 Receiving a Break Character265FIGURE 20-10: Send Break Character Sequence26520.3 EUSART Synchronous Master Mode26620.3.1 EUSART Synchronous Master Transmission266FIGURE 20-11: Synchronous Transmission266FIGURE 20-12: Synchronous Transmission (Through TXEN)267TABLE 20-7: Registers Associated with Synchronous Master Transmission26720.3.2 EUSART Synchronous Master Reception268FIGURE 20-13: Synchronous Reception (Master Mode, SREN)268TABLE 20-8: Registers Associated with Synchronous Master Reception26920.4 EUSART Synchronous Slave Mode27020.4.1 EUSART Synchronous Slave Transmission270TABLE 20-9: Registers Associated with Synchronous Slave Transmission27020.4.2 EUSART Synchronous Slave Reception271TABLE 20-10: Registers Associated with Synchronous Slave Reception27121.0 10-Bit Analog-to-Digital Converter (A/D) Module273Register 21-1: ADCON0: A/D Control Register273Register 21-2: ADCON1: A/D Control Register 1274Register 21-3: ADCON2: A/D Control Register 2275FIGURE 21-1: A/D Block Diagram276FIGURE 21-2: A/D Transfer Function277FIGURE 21-3: Analog Input Model27721.1 A/D Acquisition Requirements278EQUATION 21-1: Acquisition Time278EQUATION 21-2: A/D Minimum Charging Time278EQUATION 21-3: Calculating the Minimum Required Acquisition Time27821.2 Selecting and Configuring Acquisition Time27921.3 Selecting the A/D Conversion Clock279TABLE 21-1: Tad vs. Device Operating Frequencies27921.4 Operation in Power-Managed Modes28021.5 Configuring Analog Port Pins28021.6 A/D Conversions28121.7 Discharge281FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)281FIGURE 21-5: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)28121.8 Use of the ECCP2 Trigger282TABLE 21-2: Registers Associated with A/D Operation28222.0 Comparator Module283Register 22-1: CMCON: Comparator Module Control Register28322.1 Comparator Configuration284FIGURE 22-1: Comparator I/O Operating Modes28422.2 Comparator Operation28522.3 Comparator Reference285FIGURE 22-2: Single Comparator28522.3.1 External Reference Signal28522.3.2 Internal Reference Signal28522.4 Comparator Response Time28522.5 Comparator Outputs285FIGURE 22-3: Comparator Output Block Diagram28622.6 Comparator Interrupts28622.7 Comparator Operation During Sleep28622.8 Effects of a Reset28622.9 Analog Input Connection Considerations287FIGURE 22-4: Comparator Analog Input Model287TABLE 22-1: Registers Associated with Comparator Module28723.0 Comparator Voltage Reference Module28923.1 Configuring the Comparator Voltage Reference289Register 23-1: CVRCON: Comparator Voltage Reference Control Register289FIGURE 23-1: Comparator Voltage Reference Block Diagram29023.2 Voltage Reference Accuracy/Error29023.3 Operation During Sleep29023.4 Effects of a Reset29023.5 Connection Considerations290FIGURE 23-2: Comparator Voltage Reference Output Buffer Example291TABLE 23-1: Registers Associated with Comparator Voltage Reference29124.0 High/Low-Voltage Detect (HLVD)293Register 24-1: HLVDCON: High/Low-Voltage Detect Control Register29324.1 Operation294FIGURE 24-1: HLVD Module Block Diagram (with External Input)29424.2 HLVD Setup29524.3 Current Consumption29524.4 HLVD Start-up Time295FIGURE 24-2: Low-Voltage Detect Operation (VDIRMAG = 0)295FIGURE 24-3: High-Voltage Detect Operation (VDIRMAG = 1)29624.5 Applications296FIGURE 24-4: Typical Low-Voltage Detect Application29624.6 Operation During Sleep29724.7 Effects of a Reset297TABLE 24-1: Registers Associated with High/Low-Voltage Detect Module29725.0 Special Features of the CPU29925.1 Configuration Bits299TABLE 25-1: Configuration Bits and Device IDs300Register 25-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)301Register 25-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)302Register 25-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)303Register 25-4: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)(1)304Register 25-5: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)305Register 25-6: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)306Register 25-7: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)307Register 25-8: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)308Register 25-9: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)309Register 25-10: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)310Register 25-11: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)311Register 25-12: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)312Register 25-13: DEVID1: Device ID Register 1 for the PIC18F8722 Family313Register 25-14: DEVID2: Device ID Register 2 for the PIC18F8722 Family31325.2 Watchdog Timer (WDT)31425.2.1 Control Register314FIGURE 25-1: WDT Block Diagram314Register 25-15: WDTCON: Watchdog Timer Control Register315TABLE 25-2: Summary of Watchdog Timer Registers31525.3 Two-Speed Start-up31625.3.1 Special Considerations for Using Two-Speed Start-up316FIGURE 25-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)31625.4 Fail-Safe Clock Monitor317FIGURE 25-3: FSCM Block Diagram31725.4.1 FSCM and the Watchdog Timer31725.4.2 Exiting Fail-Safe Operation317FIGURE 25-4: FSCM Timing Diagram31825.4.3 FSCM Interrupts in Power-Managed Modes31825.4.4 POR or Wake From Sleep31825.5 Program Verification and Code Protection319FIGURE 25-5: Code-Protected Program Memory for the PIC18F8722 Family319TABLE 25-3: Summary of Code Protection Registers32025.5.1 Program Memory Code Protection320FIGURE 25-6: Table Write (WRTn) Disallowed320FIGURE 25-7: External Block Table Read (EBTRn) Disallowed321FIGURE 25-8: External Block Table Read (EBTRn) Allowed32125.5.2 Data EEPROM Code Protection32225.5.3 Configuration Register Protection32225.6 ID Locations32225.7 In-Circuit Serial Programming32225.8 In-Circuit Debugger322TABLE 25-4: Debugger Resources32225.9 Single-Supply ICSP Programming32226.0 Instruction Set Summary32326.1 Standard Instruction Set323TABLE 26-1: Opcode Field Descriptions324FIGURE 26-1: General Format for Instructions325TABLE 26-2: PIC18FXXXX Instruction Set32626.1.1 Standard Instruction Set32926.2 Extended Instruction Set36526.2.1 Extended Instruction Syntax365TABLE 26-3: Extensions to the PIC18 Instruction Set36526.2.2 Extended Instruction Set36626.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode37026.2.4 Considerations When Enabling the Extended Instruction Set37026.2.5 Special Considerations with Microchip MPLAB® IDE Tools37227.0 Development Support37327.1 MPLAB Integrated Development Environment Software37327.2 MPASM Assembler37427.3 MPLAB C18 and MPLAB C30 C Compilers37427.4 MPLINK Object Linker/ MPLIB Object Librarian37427.5 MPLAB ASM30 Assembler, Linker and Librarian37427.6 MPLAB SIM Software Simulator37427.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator37527.8 MPLAB REAL ICE In-Circuit Emulator System37527.9 MPLAB ICD 2 In-Circuit Debugger37527.10 MPLAB PM3 Device Programmer37527.11 PICSTART® Plus Development Programmer37627.12 PICkit™ 2 Development Programmer37627.13 Demonstration, Development and Evaluation Boards37628.0 Electrical Characteristics377Absolute Maximum Ratings(†)377FIGURE 28-1: PIC18F8722 Device Family Voltage-Frequency Graph (Industrial)378FIGURE 28-2: PIC18F8722 Device Family Voltage-Frequency Graph (Extended)378FIGURE 28-3: PIC18LF8722 Device Family Voltage-Frequency Graph (Industrial)37928.1 DC Characteristics: Supply Voltage PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial)38028.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial)38128.3 DC Characteristics: PIC18F8722 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial)393TABLE 28-1: Memory Programming Requirements395TABLE 28-2: Comparator Specifications396TABLE 28-3: Comparator Voltage Reference Specifications396FIGURE 28-4: High/Low-Voltage Detect Characteristics397TABLE 28-4: High/Low-Voltage Detect Characteristics39728.4 AC (Timing) Characteristics39828.4.1 Timing Parameter Symbology39828.4.2 Timing Conditions399TABLE 28-5: Temperature and Voltage Specifications – AC399FIGURE 28-5: Load Conditions for Device Timing Specifications39928.4.3 Timing Diagrams and Specifications400FIGURE 28-6: External Clock Timing (All Modes Except PLL)400TABLE 28-6: External Clock Timing Requirements400TABLE 28-7: PLL Clock Timing Specifications (Vdd = 4.2V to 5.5V)401TABLE 28-8: AC Characteristics: Internal RC Accuracy PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial)401FIGURE 28-7: CLKO and I/O Timing402TABLE 28-9: CLKO and I/O Timing Requirements402FIGURE 28-8: Program Memory Read Timing Diagram403TABLE 28-10: CLKO and I/O Timing Requirements403FIGURE 28-9: Program Memory Write Timing Diagram404TABLE 28-11: Program Memory Write Timing Requirements404FIGURE 28-10: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing405FIGURE 28-11: Brown-out Reset Timing405TABLE 28-12: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements405FIGURE 28-12: Timer0 and Timer1 External Clock Timings406TABLE 28-13: Timer0 and Timer1 External Clock Requirements406FIGURE 28-13: Capture/Compare/PWM Timings (All ECCP/CCP Modules)407TABLE 28-14: Capture/Compare/PWM Requirements (All ECCP/CCP Modules)407FIGURE 28-14: Parallel Slave Port Timing (PIC18F8527/8622/8627/8722)408TABLE 28-15: Parallel Slave Port Requirements (PIC18F8527/8622/8627/8722)408FIGURE 28-15: Example SPI Master Mode Timing (CKE = 0)409TABLE 28-16: Example SPI Mode Requirements (Master Mode, CKE = 0)409FIGURE 28-16: Example SPI Master Mode Timing (CKE = 1)410TABLE 28-17: Example SPI Mode Requirements (Master Mode, CKE = 1)410FIGURE 28-17: Example SPI Slave Mode Timing (CKE = 0)411TABLE 28-18: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)411FIGURE 28-18: Example SPI Slave Mode Timing (CKE = 1)412TABLE 28-19: Example SPI Slave Mode Requirements (CKE = 1)412FIGURE 28-19: I2C™ Bus Start/Stop Bits Timing413TABLE 28-20: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)413FIGURE 28-20: I2C™ Bus Data Timing413TABLE 28-21: I2C™ Bus Data Requirements (Slave Mode)414FIGURE 28-21: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms415TABLE 28-22: Master SSP I2C™ Bus Start/Stop Bits Requirements415FIGURE 28-22: Master SSP I2C™ Bus Data Timing415TABLE 28-23: Master SSP I2C™ Bus Data Requirements416FIGURE 28-23: EUSART Synchronous Transmission (Master/Slave) Timing417TABLE 28-24: EUSART Synchronous Transmission Requirements417FIGURE 28-24: EUSART Synchronous Receive (Master/Slave) Timing417TABLE 28-25: EUSART Synchronous Receive Requirements417TABLE 28-26: A/D Converter Characteristics: PIC18F6X27/6X22/8X27/8X22 (Industrial) PIC18LF6X27/6X22/8X27/8X22 (Industrial)418FIGURE 28-25: A/D Conversion Timing418TABLE 28-27: A/D Conversion Requirements41929.0 Packaging Information42129.1 Package Marking Information42129.2 Package Details422Appendix A: Revision History427Revision A (September 2004)427Revision B (December 2004)427Revision C (October 2008)427Appendix B: Device Differences427TABLE B-1: Device Differences (PIC18F6527/6622/6627/6722)427TABLE B-2: Device Differences (PIC18F8527/8622/8627/8722)427Appendix C: Conversion Considerations428Appendix D: Migration From Baseline to Enhanced Devices428Appendix E: Migration From Mid-Range to Enhanced Devices429Appendix F: Migration From High-End to Enhanced Devices429INDEX431The Microchip Web Site443Customer Change Notification Service443Customer Support443Reader Response444PIC18F8722 Family Product Identification System445Worldwide Sales and Service446Размер: 6,7 МБСтраницы: 446Язык: EnglishПросмотреть
Техническая СпецификацияСодержаниеFlexible Oscillator Structure:1Peripheral Highlights:1Peripheral Highlights (continued):1External Memory Bus (80-pin devices only):1Special Microcontroller Features:1Pin Diagrams2Pin Diagrams (Continued)3Table of Contents4Most Current Data Sheet5Errata5Customer Notification System51.0 Device Overview71.1 Core Features71.1.1 Technology71.1.2 Oscillator Options and Features71.1.3 Expanded Memory71.1.4 External Memory Bus71.1.5 Extended Instruction Set71.1.6 Easy Migration81.2 Other Special Features81.3 Details on Individual Family Members8TABLE 1-1: Device Features for the PIC18F6XJ1X (64-pin Devices)9TABLE 1-2: Device Features for the PIC18F8XJ1X (80-pin Devices)9FIGURE 1-1: PIC18F6XJ1X (64-pin) Block Diagram10FIGURE 1-2: PIC18F8XJ1X (80-pin) Block Diagram11TABLE 1-3: PIC18F6XJ1X Pinout I/O Descriptions12TABLE 1-4: PIC18F8XJ1X Pinout I/O Descriptions202.0 Guidelines for Getting Started with PIC18FJ Microcontrollers312.1 Basic Connection Requirements31FIGURE 2-1: Recommended Minimum connections312.2 Power Supply Pins322.3 Master Clear (MCLR) Pin32FIGURE 2-2: Example of MCLR Pin Connections322.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)33FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap33TABLE 2-1: Suitable Capacitor Equivalents33FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics342.5 ICSP Pins342.6 External Oscillator Pins352.7 Unused I/Os35FIGURE 2-5: Suggested Placement of the Oscillator Circuit353.0 Oscillator Configurations373.1 Oscillator Types37FIGURE 3-1: PIC18F87J11 Family Clock Diagram373.2 Control Registers38Register 3-1: OSCCON: Oscillator Control Register(1)38Register 3-2: OSCTUNE: Oscillator Tuning Register393.3 Clock Sources and Oscillator Switching393.3.1 Clock Source Selection403.3.2 Oscillator Transitions403.4 External Oscillator Modes413.4.1 Crystal Oscillator/Ceramic Resonators (HS Modes)41TABLE 3-1: Capacitor Selection for Ceramic Resonators41TABLE 3-2: Capacitor Selection for Crystal Oscillator41FIGURE 3-2: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)413.4.2 External Clock Input (EC Modes)42FIGURE 3-3: External Clock Input Operation (EC Configuration)42FIGURE 3-4: External Clock Input Operation (HS OSC Configuration)423.4.3 PLL Frequency Multiplier42FIGURE 3-5: PLL Block Diagram423.5 Internal Oscillator Block433.5.1 INTIO Modes43FIGURE 3-6: INTIO1 Oscillator Mode43FIGURE 3-7: INTIO2 Oscillator Mode433.5.2 INTPLL Modes433.5.3 Internal Oscillator Output Frequency and Tuning443.5.4 INTOSC Frequency Drift443.6 Reference Clock Output44Register 3-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER453.7 Effects of Power-Managed Modes on the Various Clock Sources463.8 Power-up Delays46TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode464.0 Power-Managed Modes474.1 Selecting Power-Managed Modes474.1.1 Clock Sources474.1.2 Entering Power-Managed Modes47TABLE 4-1: Power-Managed Modes474.1.3 Clock Transitions and Status Indicators484.1.4 Multiple Sleep Commands484.2 Run Modes484.2.1 PRI_RUN Mode484.2.2 SEC_RUN Mode48FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode49FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)494.2.3 RC_RUN Mode50FIGURE 4-3: Transition Timing to RC_RUN Mode50FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode504.3 Sleep Mode514.4 Idle Modes51FIGURE 4-5: Transition Timing for Entry to Sleep Mode51FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)514.4.1 PRI_IDLE Mode524.4.2 SEC_IDLE Mode52FIGURE 4-7: Transition Timing for Entry to Idle Mode52FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode524.4.3 RC_IDLE Mode534.5 Exiting Idle and Sleep Modes534.5.1 Exit By Interrupt534.5.2 Exit By WDT Time-out534.5.3 Exit By Reset534.5.4 Exit Without an Oscillator Start-up Delay535.0 Reset555.1 RCON Register55FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit55Register 5-1: RCON: Reset Control Register565.2 Master Clear (MCLR)575.3 Power-on Reset (POR)575.4 Brown-out Reset (BOR)57FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)575.4.1 Detecting BOR575.5 Configuration Mismatch (CM)575.6 Power-up Timer (PWRT)585.6.1 Time-out Sequence58TABLE 5-1: Time-out in Various Situations58FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)58FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 159FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 259FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)595.7 Reset State of Registers60TABLE 5-2: Status Bits, Their Significance and the Initialization Condition for RCON Register60TABLE 5-3: Initialization Conditions for All Registers(4)616.0 Memory Organization676.1 Program Memory Organization67FIGURE 6-1: Memory Maps for PIC18F87J11 Family Devices676.1.1 Hard Memory Vectors68FIGURE 6-2: Hard Vector and Configuration Word Locations for PIC18F87J11 Family Devices686.1.2 Flash Configuration Words68TABLE 6-1: Flash Configuration Word for PIC18F87J11 Family Devices686.1.3 PIC18F8xJ11/8XJ16 Program Memory Modes69Register 6-1: CONFIG3L: Configuration Register 3 Low696.1.4 Extended Microcontroller Mode and Address Shifting70FIGURE 6-3: Memory Maps for PIC18F87J11 Family Program Memory Modes70TABLE 6-2: Memory Access for PIC18F8X11/8616 Program Memory Modes706.1.5 Program Counter716.1.6 Return Address Stack71FIGURE 6-4: Return Address Stack and Associated Registers71Register 6-2: STKPTR: Stack Pointer Register726.1.7 Fast Register Stack73EXAMPLE 6-1: Fast Register Stack Code Example736.1.8 Look-up Tables in Program Memory73EXAMPLE 6-2: Computed GOTO Using an Offset Value736.2 PIC18 Instruction Cycle746.2.1 Clocking Scheme746.2.2 Instruction Flow/Pipelining74FIGURE 6-5: Clock/ Instruction Cycle74EXAMPLE 6-3: Instruction Pipeline Flow746.2.3 Instructions in Program Memory75FIGURE 6-6: Instructions in Program Memory756.2.4 Two-Word Instructions75EXAMPLE 6-4: Two-Word Instructions756.3 Data Memory Organization766.3.1 Bank Select Register76FIGURE 6-7: Data Memory Map for PIC18F87J11 Family Devices77FIGURE 6-8: Use of the Bank Select Register (Direct Addressing)786.3.2 Access Bank786.3.3 General Purpose Register File786.3.4 Special Function Registers79TABLE 6-3: Special Function Register Map for PIC18F87J11 Family Devices79TABLE 6-4: Shared SFR Addresses for PIC18F87J11 Family Devices80Register 6-3: WDTCON: Watchdog Timer Control Register81TABLE 6-5: Register File Summary (PIC18F87J11 Family)826.3.5 STATUS Register87Register 6-4: Status Register876.4 Data Addressing Modes886.4.1 Inherent and Literal Addressing886.4.2 Direct Addressing886.4.3 Indirect Addressing88EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing88FIGURE 6-9: Indirect Addressing896.5 Program Memory and the Extended Instruction Set916.6 Data Memory and the Extended Instruction Set916.6.1 Indexed Addressing with Literal Offset916.6.2 Instructions Affected By Indexed Literal Offset Mode91FIGURE 6-10: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)926.6.3 Mapping the Access Bank in Indexed Literal Offset Mode936.6.4 BSR in Indexed Literal Offset Mode93FIGURE 6-11: Remapping the Access Bank with Indexed Literal Offset Addressing937.0 Flash Program Memory957.1 Table Reads and Table Writes95FIGURE 7-1: TABLE READ Operation95FIGURE 7-2: Table Write Operation967.2 Control Registers967.2.1 EECON1 and EECON2 Registers96Register 7-1: EECON1: EEPROM Control Register 1977.2.2 Table Latch Register (TABLAT)987.2.3 Table Pointer Register (TBLPTR)987.2.4 Table Pointer Boundaries98TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions98FIGURE 7-3: Table Pointer Boundaries Based on Operation987.3 Reading the Flash Program Memory99FIGURE 7-4: Reads from Flash Program Memory99EXAMPLE 7-1: Reading a Flash Program Memory Word997.4 Erasing Flash Program Memory1007.4.1 Flash Program Memory Erase Sequence100EXAMPLE 7-2: Erasing a Flash Program Memory Row1007.5 Writing to Flash Program Memory101FIGURE 7-5: Table Writes to Flash Program Memory1017.5.1 Flash Program Memory Write Sequence101EXAMPLE 7-3: Writing to Flash Program Memory1027.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING).103EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY1037.5.3 Write Verify1047.5.4 Unexpected Termination of Write Operation1047.6 Flash Program Operation During Code Protection104TABLE 7-2: Registers Associated with Program Flash Memory1048.0 External Memory Bus105TABLE 8-1: PIC18F87J11 Family External Bus – I/O Port Functions1058.1 External Memory Bus Control106Register 8-1: MEMCON: External Memory Bus Control Register1068.2 Address and Data Width1078.2.1 Address Shifting on the External Bus1078.2.2 21-bit Addressing107TABLE 8-2: Address and Data Lines for Different Address and Data Widths1078.3 Wait States1088.4 Port Pin Weak Pull-ups1088.5 Program Memory Modes and the External Memory Bus1088.6 16-Bit Data Width Modes1088.6.1 16-Bit Byte Write Mode109FIGURE 8-1: 16-bit Byte Write Mode Example1098.6.2 16-Bit Word Write Mode110FIGURE 8-2: 16-bit Word Write Mode Example1108.6.3 16-Bit Byte Select Mode111FIGURE 8-3: 16-bit Byte Select Mode Example1118.6.4 16-Bit Mode Timing112FIGURE 8-4: External Memory Bus Timing for TBLRD (Extended Microcontroller Mode)112FIGURE 8-5: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)1128.7 8-Bit Data Width Mode113FIGURE 8-6: 8-bit Multiplexed Mode Example1138.7.1 8-bit Mode Timing114FIGURE 8-7: External Memory Bus Timing For TBLRD (Extended Microcontroller Mode)114FIGURE 8-8: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)1148.8 Operation in Power-Managed Modes1159.0 8 X 8 Hardware Multiplier1179.1 Introduction1179.2 Operation117EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine117EXAMPLE 9-2: 8 x 8 Signed Multiply Routine117TABLE 9-1: Performance Comparison for Various Multiply Operations117EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm118EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine118EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm118EXAMPLE 9-4: 16 x 16 Signed Multiply Routine11810.0 Interrupts119FIGURE 10-1: PIC18F87J11 Family Interrupt Logic12010.1 INTCON Registers121Register 10-1: INTCON: Interrupt Control Register121Register 10-2: INTCON2: Interrupt Control Register 2122Register 10-3: INTCON3: Interrupt Control Register 312310.2 PIR Registers124Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1124Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2125Register 10-6: PIR3: Peripheral Interrupt Request (Flag) Register 312610.3 PIE Registers127Register 10-7: PIE1: Peripheral Interrupt Enable Register 1127Register 10-8: PIE2: Peripheral Interrupt Enable Register 2128Register 10-9: PIE3: Peripheral Interrupt Enable Register 312910.4 IPR Registers130Register 10-10: IPR1: Peripheral Interrupt Priority Register 1130Register 10-11: IPR2: Peripheral Interrupt Priority Register 2131Register 10-12: IPR3: Peripheral Interrupt Priority Register 313210.5 RCON Register133Register 10-13: RCON: Reset Control Register13310.6 INTx Pin Interrupts13410.7 TMR0 Interrupt13410.8 PORTB Interrupt-on-Change13410.9 Context Saving During Interrupts134EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM13411.0 I/O Ports135FIGURE 11-1: Generic I/O Port Operation13511.1 I/O Port Pin Capabilities13511.1.1 Input Pins and Voltage Considerations135TABLE 11-1: Input Voltage Levels13511.1.2 Pin Output Drive135TABLE 11-2: Output Drive Levels13611.1.3 Pull-up Configuration13611.1.4 Interfacing to a 5V System136FIGURE 11-2: +5V System Hardware Interface136EXAMPLE 11-1: Communicating with the +5V System13611.1.5 Open-Drain Outputs137FIGURE 11-3: Using the Open-Drain Output (EUSARTx Shown as Example)13711.1.6 TTL Input Buffer Option137Register 11-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL Register 1138Register 11-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL Register 2138Register 11-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL Register 3138Register 11-4: PADCFG1: I/O Pad Configuration Control Register13911.2 PORTA, TRISA and LATA Registers140TABLE 11-3: Function of RA<7:6> in INTIO and INTPLL Modes140EXAMPLE 11-2: Initializing PORTA140TABLE 11-4: PORTA Functions141TABLE 11-5: Summary of Registers Associated with PORTA14211.3 PORTB, TRISB and LATB Registers143EXAMPLE 11-3: Initializing PORTB143TABLE 11-6: PORTB Functions144TABLE 11-7: Summary of Registers Associated with PORTB14511.4 PORTC, TRISC and LATC Registers146EXAMPLE 11-4: Initializing PORTC146TABLE 11-8: PORTC Functions147TABLE 11-9: Summary of Registers Associated with PORTC14811.5 PORTD, TRISD and LATD Registers149EXAMPLE 11-5: Initializing PORTD149TABLE 11-10: PORTD Functions150TABLE 11-11: Summary of Registers Associated with PORTD15111.6 PORTE, TRISE and LATE Registers152EXAMPLE 11-6: Initializing PORTE152TABLE 11-12: PORTE Functions153TABLE 11-13: Summary of Registers Associated with PORTE15411.7 PORTF, LATF and TRISF Registers155EXAMPLE 11-7: Initializing PORTF155TABLE 11-14: PORTF Functions156TABLE 11-15: Summary of Registers Associated with PORTF15711.8 PORTG, TRISG and LATG Registers158EXAMPLE 11-8: Initializing PORTG158TABLE 11-16: PORTG Functions159TABLE 11-17: Summary of Registers Associated with PORTG16011.9 PORTH, LATH and TRISH Registers161EXAMPLE 11-9: Initializing PORTH161TABLE 11-18: PORTH Functions162TABLE 11-19: Summary of Registers Associated with PORTH16311.10 PORTJ, TRISJ and LATJ Registers164EXAMPLE 11-10: Initializing PORTJ164TABLE 11-20: PORTJ Functions165TABLE 11-21: Summary of Registers Associated with PORTJ16512.0 Parallel Master Port167FIGURE 12-1: PMP Module Overview16712.1 Module Registers16812.1.1 Control Registers168Register 12-1: PMCONH: Parallel Port Control High Byte Register168Register 12-2: PMCONL: Parallel Port Control Low Byte Register169Register 12-3: PMMODEH: Parallel Port Mode High Byte Register170Register 12-4: PMMODEL: Parallel Port Mode Low Byte Register171Register 12-5: PMEH: Parallel Port Enable High Byte Register171Register 12-6: PMEL: Parallel Port Enable Low Byte Register172Register 12-7: PMSTATH: Parallel Port Status High Byte Register172Register 12-8: PMSTATL: Parallel Port Status Low Byte Register17312.1.2 Data Registers17412.1.3 Pad Configuration Control Register174Register 12-9: PMADDRH: Parallel Port Address Register, High Byte (Master Modes Only)(1)17412.1.4 PMP Multiplexing Options (80-pin Devices)175TABLE 12-1: PMP Pin Multiplexing for 80-Pin Devices17512.2 Slave Port Modes17512.2.1 Legacy Mode (PSP)175FIGURE 12-2: Legacy Parallel Slave Port Example175FIGURE 12-3: Parallel Slave Port Write Waveforms176FIGURE 12-4: Parallel Slave Port Read Waveforms17612.2.2 Buffered Parallel Slave Port Mode177FIGURE 12-5: Parallel Master/Slave Connection Buffered Example17712.2.3 Addressable Parallel Slave Port Mode178TABLE 12-2: Slave Mode Buffer Addressing178FIGURE 12-6: Parallel Master/Slave Connection Addressed Buffer Example178FIGURE 12-7: Parallel Slave Port Read Waveforms179FIGURE 12-8: Parallel Slave Port Write Waveforms17912.3 Master Port Modes18012.3.1 PMP and I/O Pin Control18012.3.2 Read/Write Control18012.3.3 Data Width18012.3.4 ADDRESS MULTIPLEXING180FIGURE 12-9: Demultiplexed Addressing Mode (Separate Read and Write Strobes, Two Chip Selects)181FIGURE 12-10: Partially Multiplexed Addressing Mode (Separate Read and Write Strobes, Two Chip Selects)181FIGURE 12-11: Fully Multiplexed Addressing Mode (Separate Read and Write Strobes, Two Chip Selects)18112.3.5 Chip Select Features18212.3.6 AUTO-INCREMENT/DECREMENT18212.3.7 WAIT STATES18212.3.8 Read Operation18212.3.9 Write Operation18212.3.10 Parallel Master Port Status18212.3.11 Master Mode Timing183FIGURE 12-12: Read and Write Timing, 8-bit Data, Demultiplexed Address183FIGURE 12-13: Read Timing, 8-bit Data, Partially Multiplexed Address183FIGURE 12-14: Read Timing, 8-bit Data, Wait States Enabled, Partially Multiplexed Address184FIGURE 12-15: Write Timing, 8-bit Data, Partially Multiplexed Address184FIGURE 12-16: Write Timing, 8-bit Data, Wait States Enabled, Partially Multiplexed Address184FIGURE 12-17: Read Timing, 8-bit Data, Partially Multiplexed Address, Enable Strobe185FIGURE 12-18: Write Timing, 8-bit Data, Partially Multiplexed Address, Enable Strobe185FIGURE 12-19: Read Timing, 8-bit Data, Fully Multiplexed 16-bit Address185FIGURE 12-20: Write Timing, 8-bit Data, Fully Multiplexed 16-bit Address186FIGURE 12-21: Read Timing, 16-bit Data, Demultiplexed Address186FIGURE 12-22: Write Timing, 16-bit Data, Demultiplexed Address186FIGURE 12-23: Read Timing, 16-bit Multiplexed Data, Partially Multiplexed Address187FIGURE 12-24: Write Timing, 16-bit Multiplexed Data, Partially Multiplexed Address187FIGURE 12-25: Read Timing, 16-bit Multiplexed Data, Fully Multiplexed 16-bit Address188FIGURE 12-26: Write Timing, 16-bit Multiplexed Data, Fully Multiplexed 16-bit Address18812.4 Application Examples18912.4.1 Multiplexed Memory or Peripheral189FIGURE 12-27: Example of a Multiplexed Addressing Application18912.4.2 Partially Multiplexed Memory or Peripheral190FIGURE 12-28: Example of a Partially Multiplexed Addressing Application190FIGURE 12-29: Example of an 8-bit Multiplexed Address and Data Application19012.4.3 Parallel EEPROM Example191FIGURE 12-30: Parallel EEPROM Example (Up to 15-bit Address, 8-bit Data)191FIGURE 12-31: Parallel EEPROM Example (Up to 15-bit Address, 16-bit Data)19112.4.4 LCD Controller Example192FIGURE 12-32: LCD Control Example (Byte Mode Operation)192TABLE 12-3: Registers Associated with PMP Module19213.0 Timer0 Module193Register 13-1: T0CON: Timer0 Control Register19313.1 Timer0 Operation19413.2 Timer0 Reads and Writes in 16-Bit Mode194FIGURE 13-1: Timer0 Block Diagram (8-bit Mode)194FIGURE 13-2: Timer0 Block Diagram (16-bit Mode)19413.3 Prescaler19513.3.1 Switching Prescaler Assignment19513.4 Timer0 Interrupt195TABLE 13-1: Registers Associated with Timer019514.0 Timer1 Module197Register 14-1: T1CON: Timer1 Control Register(1)19714.1 Timer1 Operation198FIGURE 14-1: Timer1 Block Diagram198FIGURE 14-2: Timer1 Block Diagram (16-bit Read/Write Mode)19814.2 Timer1 16-Bit Read/Write Mode19914.3 Timer1 Oscillator199FIGURE 14-3: External Components for the Timer1 LP Oscillator199TABLE 14-1: Capacitor Selection for the Timer Oscillator(2,3,4)19914.3.1 Using Timer1 as a Clock Source19914.3.2 Timer1 Oscillator Layout Considerations199FIGURE 14-4: Oscillator Circuit with Grounded Guard Ring20014.4 Timer1 Interrupt20014.5 Resetting Timer1 Using the ECCPx Special Event Trigger20014.6 Using Timer1 as a Real-Time Clock20014.7 Considerations in Asynchronous Counter Mode201EXAMPLE 14-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service201TABLE 14-2: Registers Associated with Timer1 as a Timer/Counter20215.0 Timer2 Module20315.1 Timer2 Operation203Register 15-1: T2CON: Timer2 Control Register20315.2 Timer2 Interrupt20415.3 Timer2 Output204FIGURE 15-1: Timer2 Block Diagram204TABLE 15-1: Registers Associated with Timer2 as a Timer/Counter20416.0 Timer3 Module205Register 16-1: T3CON: Timer3 Control Register20516.1 Timer3 Operation206FIGURE 16-1: Timer3 Block Diagram206FIGURE 16-2: Timer3 Block Diagram (16-bit Read/Write Mode)20616.2 Timer3 16-Bit Read/Write Mode20716.3 Using the Timer1 Oscillator as the Timer3 Clock Source20716.4 Timer3 Interrupt20716.5 Resetting Timer3 Using the ECCPx Special Event Trigger207TABLE 16-1: Registers Associated with Timer3 as a Timer/Counter20717.0 Timer4 Module20917.1 Timer4 Operation209Register 17-1: T4CON: Timer4 Control Register20917.2 Timer4 Interrupt21017.3 Output of TMR4210FIGURE 17-1: Timer4 Block Diagram210TABLE 17-1: Registers Associated with Timer4 as a Timer/Counter21018.0 Capture/Compare/PWM (CCP) Modules211Register 18-1: CCPxCON: CCPx Control Register (CCP4 Module, CCP5 Module)21118.1 CCP Module Configuration21218.1.1 CCP Modules and Timer Resources212TABLE 18-1: CCP Mode – Timer Resource21218.1.2 OPEN-DRAIN OUTPUT OPTION212FIGURE 18-1: ECCPx/CCPx and Timer Interconnect Configurations21218.2 Capture Mode21318.2.1 CCP Pin Configuration21318.2.2 Timer1/Timer3 Mode Selection21318.2.3 Software Interrupt21318.2.4 CCP Prescaler213EXAMPLE 18-1: Changing Between Capture Prescalers (CCP5 Shown)213FIGURE 18-2: Capture Mode Operation Block Diagram21318.3 Compare Mode21418.3.1 CCP Pin Configuration21418.3.2 Timer1/Timer3 Mode Selection21418.3.3 Software Interrupt Mode214FIGURE 18-3: Compare Mode Operation Block Diagram214TABLE 18-2: Registers Associated with Capture, Compare, Timer1 and Timer321518.4 PWM Mode216FIGURE 18-4: Simplified PWM Block Diagram216FIGURE 18-5: PWM Output21618.4.1 PWM Period216EQUATION 18-1:21618.4.2 PWM Duty Cycle216EQUATION 18-2:216EQUATION 18-3:21718.4.3 Setup for PWM Operation217TABLE 18-3: Example PWM Frequencies and Resolutions at 40 MHz217TABLE 18-4: Registers Associated with PWM, Timer2 and Timer421819.0 Enhanced Capture/ Compare/PWM (ECCP) Module219Register 19-1: CCPxCON: ECCPx Control Register (ECCP1/ECCP2/ECCP3)21919.1 ECCP Outputs and Configuration22019.1.1 ECCP1/ECCP3 Outputs and Program Memory Mode22019.1.2 ECCP2 Outputs and Program Memory Modes22019.1.3 Use of CCP4 and CCP5 with ECCP1 and ECCP322119.1.4 ECCP Modules and Timer Resources22119.1.5 OPEN-DRAIN OUTPUT OPTION221TABLE 19-1: Pin Configurations for ECCP1221TABLE 19-2: Pin Configurations for ECCP2222TABLE 19-3: Pin Configurations for ECCP322219.2 Capture and Compare Modes22319.2.1 Special Event Trigger22319.3 Standard PWM Mode22319.4 Enhanced PWM Mode22419.4.1 PWM Period224EQUATION 19-1:224FIGURE 19-1: Simplified Block Diagram of the Enhanced PWM Module22419.4.2 PWM Duty Cycle225EQUATION 19-2:225EQUATION 19-3:22519.4.3 PWM Output Configurations225TABLE 19-4: Example PWM Frequencies and Resolutions at 40 MHz225FIGURE 19-2: PWM Output Relationships (Active-High State)226FIGURE 19-3: PWM Output Relationships (Active-Low State)22619.4.4 Half-Bridge Mode227FIGURE 19-4: Half-Bridge PWM Output227FIGURE 19-5: Examples of Half-Bridge Output Mode Applications22719.4.5 Full-Bridge Mode228FIGURE 19-6: Full-Bridge PWM Output228FIGURE 19-7: Example of Full-Bridge Output Application229FIGURE 19-8: PWM Direction Change230FIGURE 19-9: PWM Direction Change at Near 100% Duty Cycle23019.4.6 Programmable Dead-Band Delay23119.4.7 Enhanced PWM Auto-Shutdown231Register 19-2: ECCPxDEL: ECCPx PWM Delay Register232Register 19-3: ECCPxAS: ECCPx Auto-Shutdown Control Register23219.4.8 Start-up Considerations233FIGURE 19-10: PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled)233FIGURE 19-11: PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Disabled)23319.4.9 Setup for PWM Operation23419.4.10 Effects of a Reset234TABLE 19-5: Registers Associated with ECCP Modules and Timer1 to Timer423520.0 Master Synchronous Serial Port (MSSP) Module23720.1 Master SSP (MSSP) Module Overview23720.2 Control Registers23720.3 SPI Mode237FIGURE 20-1: MSSPx Block Diagram (SPI Mode)23820.3.1 Registers238Register 20-1: SSPxSTAT: MSSPx Status Register (SPI Mode)239Register 20-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)24020.3.2 Operation24120.3.3 OPEN-DRAIN OUTPUT OPTION241EXAMPLE 20-1: Loading the SSP1BUF (SSP1SR) Register24120.3.4 Enabling SPI I/O24220.3.5 Typical Connection242FIGURE 20-2: SPI Master/Slave Connection24220.3.6 Master Mode243FIGURE 20-3: SPI Mode Waveform (Master Mode)24320.3.7 Slave Mode24420.3.8 Slave Select Synchronization244FIGURE 20-4: Slave Synchronization Waveform244FIGURE 20-5: SPI Mode Waveform (Slave Mode with CKE = 0)245FIGURE 20-6: SPI Mode Waveform (Slave Mode with CKE = 1)24520.3.9 Operation in Power-Managed Modes24620.3.10 Effects of a Reset24620.3.11 Bus Mode Compatibility246TABLE 20-1: SPI Bus Modes24620.3.12 SPI Clock Speed and Module Interactions246TABLE 20-2: Registers Associated with SPI Operation24720.4 I2C Mode248FIGURE 20-7: MSSPx Block Diagram (I2C™ Mode)24820.4.1 Registers248Register 20-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)249Register 20-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)250Register 20-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Master Mode)251Register 20-6: SSPxCON2: MSSPx Control Register 2 (I2C™ Slave Mode)252Register 20-7: SSPxMSK: MSSPx I2C™ Slave Address Mask Register (7-bit Masking Mode)(1)25220.4.2 Operation25320.4.3 Slave Mode253EXAMPLE 20-2: Address Masking Examples in 5-bit Masking Mode254EXAMPLE 20-3: Address Masking Examples in 7-Bit Masking Mode255FIGURE 20-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)257FIGURE 20-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)258FIGURE 20-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)259FIGURE 20-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)260FIGURE 20-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)261FIGURE 20-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)26220.4.4 Clock Stretching263FIGURE 20-14: Clock Synchronization Timing264FIGURE 20-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)265FIGURE 20-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)26620.4.5 General Call Address Support267FIGURE 20-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)26720.4.6 Master Mode268FIGURE 20-18: MSSPx Block Diagram (I2C™ Master Mode)26820.4.7 Baud Rate270FIGURE 20-19: Baud Rate Generator Block Diagram270TABLE 20-3: I2C™ Clock Rate w/BRG270FIGURE 20-20: Baud Rate Generator Timing with Clock Arbitration27120.4.8 I2C Master Mode Start Condition Timing272FIGURE 20-21: First Start Bit Timing27220.4.9 I2C Master Mode Repeated Start Condition Timing273FIGURE 20-22: Repeated Start Condition Waveform27320.4.10 I2C Master Mode Transmission27420.4.11 I2C Master Mode Reception274FIGURE 20-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Address)275FIGURE 20-24: I2C™ Master Mode Waveform (Reception, 7-bit Address)27620.4.12 Acknowledge Sequence Timing27720.4.13 Stop Condition Timing277FIGURE 20-25: Acknowledge Sequence Waveform277FIGURE 20-26: Stop Condition Receive or Transmit Mode27720.4.14 Sleep Operation27820.4.15 Effects of a Reset27820.4.16 Multi-master Mode27820.4.17 Multi -master Communication, Bus Collision and Bus Arbitration278FIGURE 20-27: Bus Collision Timing for Transmit and Acknowledge278FIGURE 20-28: Bus Collision During Start Condition (SDAx Only)279FIGURE 20-29: Bus Collision During Start Condition (SCLx = 0)280FIGURE 20-30: BRG Reset Due to SDAx Arbitration During Start Condition280FIGURE 20-31: Bus Collision During a Repeated Start Condition (Case 1)281FIGURE 20-32: Bus Collision During Repeated Start Condition (Case 2)281FIGURE 20-33: Bus Collision During a Stop Condition (Case 1)282FIGURE 20-34: Bus Collision During a Stop Condition (Case 2)282TABLE 20-4: Registers Associated with I2C™ Operation28321.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)285Register 21-1: TXSTAx: EUSARTx Transmit Status And Control Register286Register 21-2: RCSTAx: eusartx Receive Status And Control Register287Register 21-3: BAUDCONx: Baud Rate Control Register28821.1 Baud Rate Generator (BRG)28921.1.1 Operation in Power-Managed Modes28921.1.2 Sampling289TABLE 21-1: Baud Rate Formulas289EXAMPLE 21-1: Calculating Baud Rate Error290TABLE 21-2: Registers Associated with Baud Rate Generator290TABLE 21-3: Baud Rates for Asynchronous Modes29121.1.3 Auto-Baud Rate Detect293TABLE 21-4: BRG Counter Clock Rates293FIGURE 21-1: Automatic Baud Rate Calculation294FIGURE 21-2: BRG Overflow Sequence29421.2 EUSARTx Asynchronous Mode29521.2.1 EUSARTx Asynchronous Transmitter295FIGURE 21-3: EUSARTx Transmit Block Diagram295FIGURE 21-4: Asynchronous Transmission296FIGURE 21-5: Asynchronous Transmission (Back-to-Back)296TABLE 21-5: Registers Associated with Asynchronous Transmission29621.2.2 EUSARTx Asynchronous Receiver29721.2.3 Setting Up 9-bit Mode with Address Detect297FIGURE 21-6: EUSARTx Receive Block Diagram298FIGURE 21-7: Asynchronous Reception298TABLE 21-6: Registers Associated with Asynchronous Reception29921.2.4 Auto-Wake-up on Sync Break Character300FIGURE 21-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation301FIGURE 21-9: Auto-Wake-up Bit (WUE) Timings During Sleep30121.2.5 Break Character Sequence30221.2.6 Receiving A Break Character302FIGURE 21-10: Send Break Character Sequence30221.3 EUSARTx Synchronous Master Mode30321.3.1 EUSARTx Synchronous Master Transmission303FIGURE 21-11: Synchronous Transmission303FIGURE 21-12: Synchronous Transmission (Through TXEN)304TABLE 21-7: Registers Associated with Synchronous Master Transmission30421.3.2 EUSARTx Synchronous Master Reception305FIGURE 21-13: Synchronous Reception (Master Mode, SREN)305TABLE 21-8: Registers Associated with Synchronous Master Reception30521.4 EUSARTx Synchronous Slave Mode30621.4.1 EUSARTx Synchronous Slave Transmission306TABLE 21-9: Registers Associated with Synchronous Slave Transmission30621.4.2 EUSARTx Synchronous Slave Reception307TABLE 21-10: Registers Associated with Synchronous Slave Reception30722.0 10-Bit Analog-to-Digital Converter (A/D) Module309Register 22-1: ADCON0: A/D Control Register 0(1)309Register 22-2: ADCON1: A/D Control Register 1(1)310Register 22-3: ANCON0: A/D Port Configuration Register 0311Register 22-4: ANCON1: A/D Port Configuration Register 1311FIGURE 22-1: A/D Block Diagram312FIGURE 22-2: Analog Input Model31322.1 A/D Acquisition Requirements314EQUATION 22-1: Acquisition Time314EQUATION 22-2: A/D Minimum Charging Time314EQUATION 22-3: Calculating the Minimum Required Acquisition Time31422.2 Selecting and Configuring Automatic Acquisition Time31522.3 Selecting the A/D Conversion Clock315TABLE 22-1: Tad vs. Device Operating Frequencies31522.4 Configuring Analog Port Pins31522.5 A/D Conversions31622.6 Use of the ECCP2 Trigger316FIGURE 22-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)316FIGURE 22-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)31622.7 A/D Converter Calibration31722.8 Operation in Power-Managed Modes317EXAMPLE 22-1: Sample A/D Calibration Routine317TABLE 22-2: Summary of A/D Registers31823.0 Comparator Module31923.1 Registers319FIGURE 23-1: Comparator Simplified Block Diagram319Register 23-1: CMxCON: Comparatorx Control Register320Register 23-2: CMSTAT: Comparator Output Status Register32123.2 Comparator Operation322FIGURE 23-2: Single Comparator32223.3 Comparator Response Time32223.4 Analog Input Connection Considerations322FIGURE 23-3: Comparator Analog Input Model32223.5 Comparator Control and Configuration323TABLE 23-1: Comparator Inputs and Outputs32323.5.1 Comparator Enable and Input selection32323.5.2 Comparator Enable and OUtput Selection323FIGURE 23-4: Comparator I/O Configurations32423.6 Comparator Interrupts325TABLE 23-2: Comparator Interrupt Generation32523.7 Comparator Operation During Sleep32623.8 Effects of a Reset326TABLE 23-3: Registers Associated with Comparator Module32624.0 Comparator Voltage Reference Module327FIGURE 24-1: Comparator Voltage Reference Block Diagram32724.1 Configuring the Comparator Voltage Reference328Register 24-1: CVRCON: Comparator Voltage Reference Control Register32824.2 Voltage Reference Accuracy/Error32924.3 Connection Considerations32924.4 Operation During Sleep32924.5 Effects of a Reset329FIGURE 24-2: Comparator Voltage Reference Output Buffer Example329TABLE 24-1: Registers Associated with Comparator Voltage Reference32925.0 Special Features of the CPU33125.1 Configuration Bits33125.1.1 Considerations for Configuring the PIC18F87J11 Family Devices331TABLE 25-1: Mapping of the Flash Configuration Words to the Configuration Registers332TABLE 25-2: Configuration Bits and Device IDs332Register 25-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)333Register 25-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)333Register 25-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)334Register 25-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)335Register 25-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)336Register 25-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)337Register 25-7: DEVID1: Device ID Register 1 for PIC18F87J11 Family Devices338Register 25-8: DEVID2: Device ID Register 2 for PIC18F87J11 Family Devices33825.2 Watchdog Timer (WDT)33925.2.1 Control Register339FIGURE 25-1: WDT Block Diagram339Register 25-9: WDTCON: Watchdog Timer Control Register340TABLE 25-3: Summary of Watchdog Timer Registers34025.3 On-Chip Voltage Regulator34125.3.1 Voltage Regulator Tracking Mode And Low-Voltage Detection341FIGURE 25-2: Connections for the On-chip Regulator34125.3.2 On-Chip Regulator and BOR34225.3.3 Power-up Requirements34225.3.4 OPERATION IN SLEEP MODE34225.4 Two-Speed Start-up342FIGURE 25-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)34225.4.1 Special Considerations for Using Two-Speed Start-up34325.5 Fail-Safe Clock Monitor343FIGURE 25-4: FSCM Block Diagram34325.5.1 FSCM and the Watchdog Timer343FIGURE 25-5: FSCM Timing Diagram34425.5.2 Exiting Fail-Safe Operation34425.5.3 FSCM Interrupts in Power-Managed Modes34425.5.4 POR or Wake-up From Sleep34425.6 Program Verification and Code Protection34525.6.1 Configuration Register Protection34525.7 In-Circuit Serial Programming34525.8 In-Circuit Debugger345TABLE 25-4: Debugger Resources34526.0 Instruction Set Summary34726.1 Standard Instruction Set347TABLE 26-1: Opcode Field Descriptions348FIGURE 26-1: General Format for Instructions349TABLE 26-2: PIC18F87J11 Family Instruction Set35026.1.1 Standard Instruction Set35326.2 Extended Instruction Set38926.2.1 Extended Instruction Syntax389TABLE 26-3: Extensions to the PIC18 Instruction Set38926.2.2 Extended Instruction Set39026.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode39426.2.4 Considerations When Enabling the Extended Instruction Set39426.2.5 Special Considerations with Microchip MPLAB® IDE Tools39627.0 Development Support39728.0 Electrical Characteristics401Absolute Maximum Ratings(†)401FIGURE 28-1: PIC18F87J11 Family Voltage-frequency Graph, Regulator Enabled (Industrial)402FIGURE 28-2: PIC18F87J11 family Voltage-frequency Graph, Regulator Disabled (Industrial)()40228.1 DC Characteristics: Supply Voltage PIC18F87J11 Family (Industrial)40328.2 DC Characteristics: Power-Down and Supply Current PIC18F87J11 Family (Industrial)40428.3 DC Characteristics: PIC18F87J11 Family (Industrial)412TABLE 28-1: Memory Programming Requirements414TABLE 28-2: Comparator Specifications415TABLE 28-3: Voltage Reference Specifications415TABLE 28-4: Internal Voltage Regulator Specifications41528.4 AC (Timing) Characteristics41628.4.1 Timing Parameter Symbology41628.4.2 Timing Conditions417TABLE 28-5: Temperature and Voltage Specifications – AC417FIGURE 28-3: Load Conditions for Device Timing Specifications41728.4.3 Timing Diagrams and Specifications418FIGURE 28-4: External Clock Timing418TABLE 28-6: External Clock Timing Requirements418TABLE 28-7: PLL Clock Timing Specifications (Vdd = 2.15V to 3.6V)419TABLE 28-8: Internal RC Accuracy (INTOSC and INTRC Sources)419FIGURE 28-5: CLKO and I/O Timing420TABLE 28-9: CLKO and I/O Timing Requirements420FIGURE 28-6: Program Memory Fetch Timing Diagram (8-Bit)421TABLE 28-10: Program Memory Fetch Timing Requirements (8-Bit)421FIGURE 28-7: Program Memory Read Timing Diagram422TABLE 28-11: Program Memory Read Timing Requirements422FIGURE 28-8: Program Memory Write Timing Diagram423TABLE 28-12: Program Memory Write Timing Requirements423FIGURE 28-9: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing424TABLE 28-13: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements424TABLE 28-14: Timer0 and Timer1 External Clock Timings425TABLE 28-15: Timer0 and Timer1 External Clock Requirements425FIGURE 28-10: Parallel Slave Port Timing426TABLE 28-16: Parallel Slave Port Requirements426FIGURE 28-11: Parallel Master Port Read Timing Diagram427TABLE 28-17: Parallel Master Port Read Timing Requirements427FIGURE 28-12: Parallel Master Port Write Timing Diagram428TABLE 28-18: Parallel Master Port Write Timing Requirements428FIGURE 28-13: Capture/Compare/PWM Timings (Including ECCP Modules)429TABLE 28-19: Capture/Compare/PWM Requirements (Including ECCP Modules)429FIGURE 28-14: Example SPI Master Mode Timing (CKE = 0)430TABLE 28-20: Example SPI Mode Requirements (Master Mode, Cke = 0)430FIGURE 28-15: Example SPI Master Mode Timing (CKE = 1)431TABLE 28-21: Example SPI Mode Requirements (Master Mode, CKE = 1)431FIGURE 28-16: Example SPI Slave Mode Timing (CKE = 0)432TABLE 28-22: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)432FIGURE 28-17: Example SPI Slave Mode Timing (CKE = 1)433TABLE 28-23: Example SPI Slave Mode Requirements (CKE = 1)433FIGURE 28-18: I2C™ Bus Start/Stop Bits Timing434TABLE 28-24: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)434FIGURE 28-19: I2C™ Bus Data Timing434TABLE 28-25: I2C™ Bus Data Requirements (Slave Mode)435FIGURE 28-20: MSSPx I2C™ Bus Start/Stop Bits Timing Waveforms436TABLE 28-26: MSSPx I2C™ Bus Start/Stop Bits Requirements436FIGURE 28-21: MSSPx I2C™ Bus Data Timing436TABLE 28-27: MSSPx I2C™ Bus Data Requirements437FIGURE 28-22: EUSARTx Synchronous Transmission (Master/Slave) Timing438TABLE 28-28: EUSARTx Synchronous Transmission Requirements438FIGURE 28-23: EUSARTx Synchronous Receive (Master/Slave) Timing438TABLE 28-29: EUSARTx Synchronous Receive Requirements438TABLE 28-30: A/D Converter Characteristics: PIC18F87J11 Family (Industrial)439FIGURE 28-24: A/D Conversion Timing439TABLE 28-31: A/D Conversion Requirements44029.0 Packaging Information44129.1 Package Marking Information44129.2 Package Details442Appendix A: Revision History447Revision A (January 2007)447Revision B (February 2007)447Revision C (January 2008)447Revision D (October 2009)447Revision E (June 2012)447Appendix B: Device Differences447TABLE B-1: DEVICE DIFFERENCES BETWEEN PIC18F87J11 Family MEMBERS447The Microchip Web Site449Customer Change Notification Service449Customer Support449Reader Response450INDEX451Product Identification System463Worldwide Sales and Service466Размер: 7,2 МБСтраницы: 466Язык: EnglishПросмотреть
