Инструкции для Motorola CPCI-6020

Содержание

• CPCI-6020 CompactPCI Single Board Computer

  1
• Contents

  3
• List of Tables

  9
• List of Figures

  11
• About this Manual

  13
  • Overview of Contents

    13
  • Abbreviations

    14
  • Conventions

    15
  • Summary of Changes

    16
  • Comments and Suggestions

    17
• Safety Notes

  19
• Sicherheitshinweise

  25
• Introduction

  31
  • 1.1 Features

    31
  • 1.2 Standard Compliances

    32
  • 1.3 Ordering Information

    33
    • 1.3.1 Supported Board Models

      33
    • 1.3.2 Board Accessories

      34
• Hardware Preparation and Installation

  35
  • 2.1 Overview

    35
  • 2.2 Unpacking and Inspecting the Board

    35
  • 2.3 Overview of Start-up Procedure

    36
  • 2.4 Equipment Required

    37
  • 2.5 Environmental and Power Requirements

    37
    • 2.5.1 Environmental Requirements

      37
    • 2.5.2 Power Requirements

      39
    • 2.5.3 Thermal Requirements

      39
  • 2.6 Hardware Configuration

    39
  • 2.7 CPCI-6020 Baseboard Preparation

    40
  • 2.8 Jumper Settings

    41
    • 2.8.1 Flash Bank Selection

      41
    • 2.8.2 Harrier Power Up Configuration Header

      42
    • 2.8.3 PMC 66 MHz Disable

      42
    • 2.8.4 Enable/Disable +12 V and -12 V Use

      42
    • 2.8.5 Enable/Disable Lockdown of One or More Flash Blocks for Bank A

      43
    • 2.8.6 Enable Write-Protect for Entire Flash on Bank A

      43
    • 2.8.7 Remote Switch

      43
  • 2.9 Hardware Installation

    43
  • 2.10 PMC Module Installation

    44
  • 2.11 CompactFlash Memory Card Installation

    46
  • 2.12 Before You Install or Remove a Board

    47
    • 2.12.1 Watch for Bent Pins or Other Damage

      48
    • 2.12.2 Use Caution When Installing or Removing Boards

      48
    • 2.12.3 Understanding Hot Swap

      48
    • 2.12.4 Recognize Different Injector/Ejector Lever Types

      49
    • 2.12.5 Verify Slot Usage

      50
    • 2.12.6 Preserve EMI Compliance

      50
  • 2.13 Installing and Removing a Module

    51
  • 2.14 Startup and Operation

    54
  • 2.15 System Considerations

    55
• Controls, LEDs, and Connectors

  57
  • 3.1 Overview

    57
  • 3.2 CPCI-6020 Baseboard Layout

    57
  • 3.3 Front Panel Connectors and LEDs

    58
    • 3.3.1 Front Panel Ethernet Port

      58
    • 3.3.2 Front Panel Asynchronous Serial Port

      59
    • 3.3.3 Front Panel USB ports

      59
    • 3.3.4 ABORT# Switch

      60
    • 3.3.5 RESET# Switch

      60
    • 3.3.6 Front Panel LEDs

      60
  • 3.4 Connector Pin Assignments

    60
    • 3.4.1 CompactPCI Bus Connectors

      60
    • 3.4.2 CompactPCI User I/O Connector

      63
    • 3.4.3 CompactPCI User I/O Connector

      64
    • 3.4.4 CompactPCI User I/O Connector

      65
    • 3.4.5 Memory Mezzanine Connectors

      67
    • 3.4.6 PCI Mezzanine Card (PMC) Connectors

      68
    • 3.4.7 Lock Down Flash Enable Jumper

      72
    • 3.4.8 PMC 66 Mhz Disable Jumper

      73
    • 3.4.9 Remote Switch Connector

      73
    • 3.4.10 Flash Write Protect Enable Jumper

      73
    • 3.4.11 Harrier Power Up Configuration

      74
    • 3.4.12 Xport Flash Bank Select Header

      74
    • 3.4.13 RISCWatch Header

      74
    • 3.4.14 Mictor Debug Connector

      75
• Functional Description

  81
  • 4.1 Overview

    81
  • 4.2 Block Diagram

    82
  • 4.3 Local PCI Bus Resources

    83
    • 4.3.1 PCI Bus A Resources

      83
      • 4.3.1.1 Local CompactPCI Bus

        83
      • 4.3.1.2 Remote (Expansion) CompactPCI Bus

        83
      • 4.3.1.3 Primary Ethernet Channel

        83
      • 4.3.1.4 ISA Bridge, Including EIDE Function

        84
      • 4.3.1.5 EIDE Interface

        84
      • 4.3.1.6 ISA Bus Resources

        84
      • 4.3.1.7 Synchronous Serial Ports

        84
      • 4.3.1.8 USB Controller

        85
  • 4.4 PCI Bus B Resources

    85
    • 4.4.1 PMC Slot

      85
    • 4.4.2 Secondary Ethernet Channel

      86
  • 4.5 Processor Bus Resources

    87
    • 4.5.1 Processor

      87
    • 4.5.2 L2 Cache

      87
  • 4.6 Harrier System Memory Controller and PCI Host Bridge ASIC

    87
    • 4.6.1 Dual Harrier Assignments

      88
    • 4.6.2 Harrier Power-Up Configuration

      88
    • 4.6.3 Debug Connector

      90
    • 4.6.4 PPC Bus Arbitration

      90
  • 4.7 ECC Memory Bus Resources

    90
    • 4.7.1 Harrier A Memory Bus

      90
    • 4.7.2 Harrier B Memory Bus

      91
    • 4.7.3 RAM500 Memory Mezzanine

      91
  • 4.8 Harrier Xport Resources

    91
    • 4.8.1 Harrier A, Channel 0 - Onboard Bank A Flash

      92
    • 4.8.2 Harrier A, Channel 1 - Socketed Bank B Flash

      92
    • 4.8.3 Harrier A, Channel 2 - NVRAM, RTC, External Register Set

      92
    • 4.8.4 Harrier A, Channel 3

      92
    • 4.8.5 Harrier B, Channel 0, 1, 2 and 3

      92
  • 4.9 Other Harrier Resources

    93
    • 4.9.1 I2C Bus Resources - Serial EEPROM

      93
    • 4.9.2 Asynchronous Serial Ports

      93
    • 4.9.3 32-Bit Timers

      93
    • 4.9.4 Watchdog Timers

      93
  • 4.10 Other Board Resources

    94
    • 4.10.1 Miscellaneous Control and Status

      94
    • 4.10.2 Clock Generator

      94
    • 4.10.3 Onboard Power Supplies

      95
    • 4.10.4 Board Reset Logic

      95
    • 4.10.5 Soft Reset

      97
    • 4.10.6 Front Panel Resources

      97
    • 4.10.7 ABORT# and RESET# Switches

      97
    • 4.10.8 On-Board LEDs

      98
    • 4.10.9 Harrier Power Up Configuration Header

      98
  • 4.11 Hot Swap Support

    98
  • 4.12 High Availability Support

    98
    • 4.12.1 HSC Bridge Board Interface

      98
    • 4.12.2 Local CompactPCI Bus Interface

      99
    • 4.12.3 Secondary Bus Arbitration

      99
    • 4.12.4 Secondary Bus Tri-Stating

      99
    • 4.12.5 System Slot Hot Swap

      99
  • 4.13 EIDE Interface

    100
  • 4.14 Ethernet Interface

    100
  • 4.15 Hot Swap Support

    100
  • 4.16 PMC Interface Module (PIM)

    100
  • 4.17 Asynchronous Serial Ports

    101
  • 4.18 Synchronous Serial Ports

    101
  • 4.19 I/O Signal Multiplexing (IOMUX)

    101
  • 4.20 Serial Interface Modules (SIM)

    103
  • 4.21 PMC Interface Module (PIM)

    103
  • 4.22 PMC Interface Module Form Factor

    104
  • 4.23 PMC Interface Connector

    105
  • 4.24 Host I/O Connector

    105
  • 4.25 Speaker Port

    105
  • 4.26 Floppy Disk Port

    105
  • 4.27 Mouse and Keyboard Port

    105
• Firmware

  107
  • 5.1 PPCBug Overview

    107
  • 5.2 PPCBug Basics

    107
  • 5.3 Memory Requirements

    108
  • 5.4 PPCBug Implementation

    108
  • 5.5 MPU, Hardware and Firmware Initialization

    108
  • 5.6 Using PPCBug

    110
  • 5.7 Debugger Commands

    110
  • 5.8 Diagnostic Tests

    114
• RAM500 Memory Expansion Module

  117
  • 6.1 Overview

    117
  • 6.2 RAM500 Description

    117
  • 6.3 RAM500 Module Installation

    118
  • 6.4 Features

    119
    • 6.4.1 SROM

      119
    • 6.4.2 Host Clock Logic

      120
    • 6.4.3 Serial Presence Detect (SPD) Data

      120
  • 6.5 RAM500 Connectors

    120
    • 6.5.1 Bottom Side Memory Expansion Connector (P1)

      120
    • 6.5.2 Top Side Memory Expansion Connector (J1)

      123
  • 6.6 RAM500 Programming Issues

    125
• Transition Module Preparation and Installation

  127
  • 7.1 Overview

    127
  • 7.2 General Description

    127
    • 7.2.1 Component Layout

      129
    • 7.2.2 Rear Panel Connectors

      130
  • 7.3 Unpacking and Inspecting the RTM

    131
  • 7.4 Preparing the Transition Module

    131
    • 7.4.1 Serial Ports 1 and 2

      131
    • 7.4.2 Serial Ports 3 and 4

      132
    • 7.4.3 Serial Interface Module Circuitry

      133
    • 7.4.4 Port Configuration

      135
  • 7.5 Installing the SIMs

    136
  • 7.6 Installing the PIM

    138
  • 7.7 Installing and Removing the Transition Module

    140
  • 7.8 Connectors and Cables

    141
  • 7.9 Connector Pin Assignments

    143
    • 7.9.1 CompactPCI Connectors

      143
    • 7.9.2 PMC I/O Module Connector

      143
    • 7.9.3 10BaseT/100BaseTx Connectors

      146
    • 7.9.4 COM1 Connector

      146
    • 7.9.5 COM2 Header

      147
    • 7.9.6 EIDE Header

      147
    • 7.9.7 Floppy Port Header

      148
    • 7.9.8 +5VDC Power Connector

      148
    • 7.9.9 Keyboard/Mouse Connector

      149
    • 7.9.10 Sync/Async Serial Ports

      149
    • 7.9.11 Speaker Output Header

      150
• CNFG and ENV Commands

  151
  • 8.1 Overview

    151
  • 8.2 CNFG - Configure Board Information

    151
  • 8.3 ENV - Set Environment

    152
  • 8.4 Configuring the PPCBug Parameters

    152
• A Related Documentation

  161
  • A.1 Embedded Communications Computing Documents

    161
  • A.2 Manufacturers’ Documents

    161
  • A.3 Related Specifications

    162
• Index

  165