Инструкции для Motorola DSP56000

Содержание

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• SECTION 1.1 INTRODUCTION

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• SECTION 1.2 ORIGIN OF DIGITAL SIGNAL PROCESSING

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• SECTION 2.1 DSP56K CENTRAL ARCHITECTURE OVERVIEW

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• SECTION 2.2 DATA BUSES

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• SECTION 3.1 DATA ARITHMETIC LOGIC UNIT

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• SECTION 3.2 OVERVIEW AND DATA ALU ARCHITECTURE

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• SECTION 4.2 AGU ARCHITECTURE

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• 4.2.1 Address Register Files (Rn)

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• SECTION 5.1 PROGRAM CONTROL UNIT

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• SECTION 5.2 OVERVIEW

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• SECTION 6.1 INSTRUCTION SET INTRODUCTION

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• SECTION 6.2 SYNTAX

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• SECTION 6.3 INSTRUCTION FORMATS

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• SECTION 7.1 PROCESSING STATES

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• SECTION 7.2 NORMAL PROCESSING STATE

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• 7.2.1 Instruction Pipeline

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• SECTION 8.1 PORT A OVERVIEW

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• SECTION 8.2 PORT A INTERFACE

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• SECTION 9.1 PLL CLOCK OSCILLATOR INTRODUCTION

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• SECTION 9.2 PLL COMPONENTS

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• SECTION 10.1 INTRODUCTION

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• SECTION 10.2 ON-CHIP EMULATION (OnCE) PINS

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• SECTION 11.1 USER SUPPORT

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• SECTION A.1 APPENDIX A INTRODUCTION

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• SECTION A.2 INSTRUCTION GUIDE

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• SECTION B.1 INTRODUCTION

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• SECTION B.2 BENCHMARK PROGRAMS

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• SECTION 2.3 ADDRESS BUSES

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• 4.2.2 Offset Register Files (Nn)

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• 9.2.1 Phase Detector and Charge Pump Loop Filter

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• SECTION 11.2 MOTOROLA DSP PRODUCT SUPPORT

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• 11.2.1 DSP56000CLASx Assembler/Simulator

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• 11.2.2 Macro Cross Assembler Features:

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• SECTION A.3 NOTATION

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• SECTION 2.4 DATA ALU

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• SECTION 2.5 ADDRESS GENERATION UNIT

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• SECTION 2.6 PROGRAM CONTROL UNIT

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• 3.2.1 Data ALU Input Registers (X1, X0, Y1, Y0)

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• 4.2.3 Modifier Register Files (Mn)

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• 4.2.4 Address ALU

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• SECTION 5.3 PROGRAM CONTROL UNIT (PCU) ARCHITECTURE

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• 5.3.1 Program Decode Controller

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• 5.3.2 Program Address Generator (PAG)

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• 6.3.1 Operand Sizes

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• 8.2.1 Read/Write Control Signals

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• 8.2.1.1 Program Memory Select (PS)

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• 8.2.1.2 Data Memory Select (DS)

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• 8.2.1.3 X/Y Select (X/Y)

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• 8.2.2 Port A Address and Data Bus Signals

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• 9.2.2 Voltage Controlled Oscillator (VCO)

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• 9.2.3 Frequency Multiplier

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• 9.2.4 Low Power Divider (LPD)

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• 9.2.5 PLL Control Register (PCTL)

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• 9.2.5.1 PCTL Multiplication Factor Bits (MF0-MF11) - Bits 0-11

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• 11.2.3 Simulator Features:

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• 11.2.4 DSP56KCCx Language Compiler Features:

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• SECTION 2.7 MEMORY EXPANSION PORT (PORT A)

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• SECTION 2.8 ON-CHIP EMULATOR (OnCE)

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• SECTION 2.9 PHASE-LOCKED LOOP (PLL) BASED CLOCKING

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• 3.2.2 MAC and Logic Unit

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• 4.2.5 Address Output Multiplexers

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• SECTION 4.3 PROGRAMMING MODEL

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• 5.3.3 Program Interrupt Controller

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• 5.3.4 Instruction Pipeline Format

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• 6.3.2 Data Organization in Registers

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• 6.3.2.1 Data ALU Registers

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• 8.2.2.1 Address (A0–A15)

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• 8.2.2.2 Data (D0–D23)

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• 8.2.3 Port A Bus Control Signals

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• 8.2.3.1 Read Enable (RD)

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• 8.2.3.2 Write Enable (WR)

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• 8.2.3.3 Port A Access Control Signals

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• 8.2.4 Interrupt and Mode Control

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• 8.2.5 Port A Wait States

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• 9.2.5.2 PCTL Division Factor Bits (DF0-DF3) - Bits 12-15

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• SECTION 10.3 OnCE CONTROLLER AND SERIAL INTERFACE

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• SECTION 11.3 DSP56KADSx APPLICATION DEVELOPMENT SYSTEM

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• System Hardware Features:

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• System Software Features:

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• 3.2.3 Data ALU A and B Accumulators

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• 4.3.1 Address Register Files (R0 - R3 and R4 - R7)

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• 4.3.2 Offset Register Files (N0 - N3 and N4 - N7)

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• 6.3.2.2 AGU Registers

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• 9.2.5.3 PCTL XTAL Disable Bit (XTLD) - Bit 16

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• 9.2.5.4 PCTL STOP Processing State Bit (PSTP) - Bit 17

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• SECTION 11.4 Dr. BuB ELECTRONIC BULLETIN BOARD

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• 4.3.3 Modifier Register Files (M0 - M3 and M4 - M7)

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• SECTION 4.4 ADDRESSING

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• SECTION 5.4 PROGRAMMING MODEL

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• 5.4.1 Program Counter

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• 6.3.2.3 Program Control Registers

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• 7.2.2 Summary of Pipeline-Related Restrictions

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• 9.2.5.5 PCTL PLL Enable Bit (PEN) - Bit 18

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• SECTION 1.2 SUMMARY OF DSP56K FAMILY FEATURES

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• 3.2.4 Accumulator Shifter

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• 3.2.5 Data Shifter/Limiter

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• 3.2.5.1 Limiting (Saturation Arithmetic)

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• 4.4.1 Address Register Indirect Modes

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• 4.4.1.1 No Update

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• 4.4.1.2 Postincrement By 1

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• 4.4.1.3 Postdecrement By 1

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• 5.4.2 Status Register

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• 6.3.3 Data Organization in Memory

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• 9.2.5.7 PCTL Chip Clock Source Bit (CSRC) - Bit 21

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• 9.2.5.8 PCTL CKOUT Clock Source Bit (CKOS) - Bit 22

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• 9.2.5.9 PCTL Reserved Bit - Bit 23

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• SECTION 9.3 PLL PINS

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• 3.2.5.2 Scaling

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• SECTION 3.3 DATA REPRESENTATION AND ROUNDING

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• 4.4.1.4 Postincrement By Offset Nn

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• 5.4.2.1 Carry (Bit 0)

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• 5.4.2.2 Overflow (Bit 1)

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• 5.4.2.3 Zero (Bit 2)

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• 5.4.2.4 Negative (Bit 3)

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• 5.4.2.5 Unnormalized (Bit 4)

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• SECTION 7.3 EXCEPTION PROCESSING STATE

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• SECTION A.4 ADDRESSING MODES

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• SECTION 1.3 MANUAL ORGANIZATION

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• 4.4.1.5 Postdecrement By Offset Nn

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• 5.4.2.6 Extension (Bit 5)

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• 5.4.2.7 Limit (Bit 6)

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• 5.4.2.8 Scaling Bit (Bit 7)

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• 6.3.4 Operand References

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• 6.3.4.1 Program References

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• 6.3.4.2 Stack References

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• 6.3.4.3 Register References

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• 6.3.4.4 Memory References

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• 6.3.4.4.1 X Memory References

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• SECTION 9.4 PLL OPERATION CONSIDERATIONS

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• 9.4.1 Operating Frequency

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• 9.4.2 Hardware Reset

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• SECTION 10.4 OnCE MEMORY BREAKPOINT LOGIC

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• 4.4.1.6 Indexed By Offset Nn

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• 5.4.2.9 Interrupt Masks (Bits 8 and 9)

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• 5.4.2.10 Scaling Mode (Bits 10 and 11)

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• 6.3.4.4.2 Y Memory References

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• 6.3.4.4.3 L Memory References

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• 6.3.4.4.4 YX Memory References

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• 6.3.5 Addressing Modes

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• 7.3.1 Interrupt Types

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• 7.3.2 Interrupt Priority Structure

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• 9.4.3 Operation with PLL Disabled

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• 9.4.4 Changing the MF0-MF11 Bits

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• 4.4.1.7 Predecrement By 1

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• 5.4.2.11 Reserved Status (Bit 12)

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• 5.4.2.12 Trace Mode (Bit 13)

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• 5.4.2.13 Double Precision Multiply Mode (Bit 14)

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• 5.4.2.14 Loop Flag (Bit 15)

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• 6.3.5.1 Register Direct Modes

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• 6.3.5.1.1 Data or Control Register Direct

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• 6.3.5.1.2 Address Register Direct

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• 6.3.5.2 Address Register Indirect Modes

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• 9.4.5 Change of DF0-DF3 Bits

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• 9.4.6 Loss of Lock

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• 9.4.7 STOP Processing State

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• SECTION 10.5 OnCE TRACE LOGIC

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• A.4.1 Addressing Mode Modifiers

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• 4.4.2 Address Modifier Arithmetic Types

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• 5.4.3 Operating Mode Register

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• 5.4.4 System Stack

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• 6.3.5.3 Special Addressing Modes

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• 6.3.5.3.1 Immediate Data

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• 6.3.5.3.2 Absolute Address

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• 6.3.5.3.3 Immediate Short

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• 6.3.5.3.4 Short Jump Address

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• 6.3.5.3.5 Absolute Short

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• 7.3.2.1 Interrupt Priority Levels

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• 9.4.8 CKOUT Considerations

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• 9.4.9 Synchronization Among EXTAL, CKOUT, and the Internal Clock

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• SECTION 10.6 METHODS OF ENTERING THE DEBUG MODE

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• SECTION A.5 CONDITION CODE COMPUTATION

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• 5.4.5 Stack Pointer Register

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• 7.3.2.2 Exception Priorities Within an IPL

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• SECTION A.6 PARALLEL MOVE DESCRIPTIONS

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• SECTION 3.4 DOUBLE PRECISION MULTIPLY MODE

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• 4.4.2.1 Linear Modifier (Mn=$FFFF)

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• 5.4.5.1 Stack Pointer (Bits 0–3)

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• 5.4.5.2 Stack Error Flag (Bit 4)

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• 5.4.5.3 Underflow Flag (Bit 5)

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• 6.3.5.3.6 I/O Short

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• 6.3.5.3.7 Implicit Reference

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• 7.3.3 Interrupt Sources

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• 7.3.3.1 Hardware Interrupt Sources

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• BUS REGISTER

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• SECTION 11.5 MOTOROLA DSP NEWS

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• SECTION 11.6 MOTOROLA FIELD APPLICATION ENGINEERS

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• SECTION 11.7 DESIGN HOTLINE– 1-800-521-6274

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• SECTION 11.8 DSP HELP LINE – (512) 891-3230

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• SECTION 11.9 MARKETING INFORMATION– (512) 891-2030

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• SECTION 11.11 UNIVERSITY SUPPORT – (512) 891-3098

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• 5.4.5.4 Reserved Stack Pointer Registration (Bits 6–23)

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• 5.4.6 Loop Address Register

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• 5.4.7 Loop Counter Register

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• 5.4.8 Programming Model Summary

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• 7.3.3.2 Software Interrupt Sources

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• SECTION 11.13 REFERENCE BOOKS AND MANUALS

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• SECTION A.7 INSTRUCTION DESCRIPTIONS

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• 4.4.2.2 Modulo Modifier

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• SECTION 10.8 PROGRAM ADDRESS BUS HISTORY BUFFER

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• SECTION 3.5 DATA ALU PROGRAMMING MODEL

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• SECTION 3.6 DATA ALU SUMMARY

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• SECTION 10.9 SERIAL PROTOCOL DESCRIPTION

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• REQUIREMENTS

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• 6.3.5.4 Addressing Modes Summary

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• SECTION 6.4 INSTRUCTION GROUPS

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• SECTION 10.11 USING THE OnCE

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• 4.4.2.3 Reverse-Carry Modifier (Mn=$0000)

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• 6.4.1 Arithmetic Instructions

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• 7.3.3.3 Other Interrupt Sources

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• 6.4.2 Logical Instructions

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• 6.4.3 Bit Manipulation Instructions

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• 6.4.4 Loop Instructions

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• 7.3.4 Interrupt Arbitration

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• 7.3.5 Interrupt Instruction Fetch

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• 4.4.2.4 Address-Modifier-Type Encoding Summary

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• 7.3.6 Instructions Preceding the Interrupt Instruction Fetch

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• 6.4.5 Move Instructions

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• 7.3.7 Interrupt Instruction Execution

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• 6.4.6 Program Control Instructions

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• SECTION 7.4 RESET PROCESSING STATE

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• SECTION 7.5 WAIT PROCESSING STATE

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• SECTION 7.6 STOP PROCESSING STATE

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• SECTION A.8 INSTRUCTION TIMING

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• SECTION A.9 INSTRUCTION SEQUENCE RESTRICTIONS

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• A.9.1 Restrictions Near the End of DO Loops

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• A.9.2 Other DO Restrictions

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• A.9.3 ENDDO Restrictions

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• A.9.4 RTI and RTS Restrictions

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• A.9.5 SP and SSH/SSL Manipulation Restrictions

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• A.9.6 R, N, and M Register Restrictions

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• A.9.7 Fast Interrupt Routines

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• A.9.8 REP Restrictions

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• SECTION A.10 INSTRUCTION ENCODING

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• A.10.1 Partial Encodings for Use in Instruction Encoding

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• Portion of an Instruction

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• Allow Parallel Moves

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• A.10.4 Parallel Instruction Encoding of the Operation Code

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