Инструкции для Samsung 3.5" hard disk drives

Содержание

• SCOPE

  1
• USER DEFINITION

  1
• MANUAL ORGANIZATION

  1
• TERMINOLOGY AND CONVENTIONS

  2
• REFERENCE

  3
• DESCRIPTION

  4
• INTRODUCTION

  4
• KEY FEATURES

  4
• STANDARDS AND REGULATIONS

  5
• HARDWARE REQUIREMENTS

  5
• SPECIFICATIONS

  6
• SPECIFICATION SUMMARY

  6
• PHYSICAL SPECIFICATIONS

  7
• LOGICAL CONFIGURATIONS

  7
• PERFORMANCE SPECIFICATIONS

  8
• POWER REQUIREMENTS

  9
• ENVIRONMENTAL SPECIFICATIONS

  10
• RELIABILITY SPECIFICATIONS

  11
• INSTALLATION

  12
• SPACE REQUIREMENTS

  12
• UNPACKING INSTRUCTIONS

  13
• MOUNTING

  13
• Orientation

  13
• Clearance

  15
• Ventilation

  16
• CABLE CONNECTORS

  16
• DC Power Connector

  16
• AT-Bus Interface Connector

  16
• JUMPER BLOCK CONFIGURATIONS

  18
• DRIVE INSTALLATION

  20
• SYSTEM STARTUP PROCEDURE

  21
• Drive Installation to Access the Full Capacity Using 32GB Clip

  22
• DISK DRIVE OPERATION

  23
• HEAD / DISK ASSEMBLY (HDA)

  23
• Base Casting Assembly

  23
• DC Spindle Motor Assembly

  23
• Disk Stack Assembly

  25
• Head Stack Assembly

  25
• Voice Coil Motor and Actuator Latch Assemblies

  25
• Air Filtration System

  25
• DRIVE ELECTRONICS

  26
• Digital Signal Process and Interface Controller

  26
• AT Disk Controller

  26
• The Host Interface Control Block

  28
• The Buffer Control Block

  29
• The Disk Control Block

  29
• The Disk ECC Control Block

  31
• Frequency Synthesizer

  31
• Power Management

  31
• Read/Write IC

  31
• Time Base Generator

  32
• Automatic Gain Control

  32
• Asymmetry Correction Circuitry (ASC)

  32
• Analog Anti-Aliasing Low Pass Filter

  32
• Analog to Digital Converter (ADC) and FIR

  32
• SERVO SYSTEM

  34
• READ AND WRITE OPERATIONS

  34
• The Read Channel

  34
• The Write Channel

  35
• FIRMWARE FEATURES

  35
• Read Caching

  35
• Write Caching

  36
• Defect Management

  37
• Automatic Defect Allocation

  37
• Multi-burst ECC Correction

  37
• SMART

  37
• AAM

  37
• AT INTERFACE AND ATA COMMANDS

  39
• INTRODUCTION

  39
• PHYSICAL INTERFACE

  39
• Signal Conventions

  39
• Signal Summary

  39
• Signal Descriptions

  40
• CS1FX- (Drive Chip Select 0)

  40
• CS3FX- (Drive Chip Select 1)

  40
• DA0-2 (Drive Address Bus)

  40
• DASP- (Drive Active/Slave Present)

  40
• DD0-DD15 (Drive Data Bus)

  40
• DIOR- (Drive I/O Read)

  40
• DIOW- (Drive I/O Write)

  40
• DMACK- (DMA Acknowledge)

  41
• DMARQ (DMA Request)

  41
• INTRQ (Drive Interrupt)

  41
• IOCS16- (Drive 16-bit I/O)

  41
• IORDY (I/O Channel Ready)

  42
• PDIAG- (Passed Diagnostics)

  42
• RESET- (Drive Reset)

  42
• LOGICAL INTERFACE

  46
• General

  46
• Bit Conventions

  46
• Environment

  46
• I/O Register - Address

  48
• Control Block Register Descriptions

  49
• Alternate Status Register (3F6h)

  49
• Drive Address Register (3F7h)

  49
• Device Control Register (3F6h)

  49
• Command Block Register Descriptions

  50
• Data Register (1F0h)

  50
• Features Register (1F1h)

  50
• Sector Number Register (1F3h)

  50
• Error Register (1F1h)

  50
• Sector Count Register (1F2h)

  51
• Cylinder High Register (1F5h)

  51
• Cylinder Low Register (1F4h)

  51
• Command Register (1F7h)

  51
• Drive/Head Register (1F6h)

  51
• Status Register (1F7h)

  52
• AT COMMAND REGISTER DESCRIPTIONS

  53
• Check Power Mode (98h, E5h)

  56
• Download Micro Code (92h)

  56
• Execute Device Diagnostics (90h)

  56
• Flush Cache (E7h)

  57
• Format Track (50h)

  57
• Identify Device (ECh)

  57
• Idle (97h,E3h)

  62
• Idle Immediate (95h,E1h)

  62
• Initialize Device Parameters (91h)

  62
• Read Buffer (E4h)

  63
• Read DMA (C8h:with retry, C9h:without retry)

  63
• Read Long (22h:with retry, 23h: without retry)

  63
• Read Multiple Command (C4h)

  64
• Read Native Max Address (F8h)

  65
• Read Sector(s) (20h:with retry, 21h:without retry)

  65
• Read Verify Sector(s) (40h:with retry, 41h:without retry)

  66
• Recalibrate (1xh)

  66
• Seek (7xh)

  66
• Set Features (EFh)

  67
• Set Max Address (F9h)

  69
• Set Multiple Mode (C6h)

  70
• Sleep (99h, E6h)

  70
• Standby (96h,E2h)

  71
• SMART (B0h)

  71
• Smart disable operation (D9h)

  71
• Smart enable/disable attribute autosave (D2h)

  72
• Smart enable operations (D8h)

  72
• Smart execute off-line immediate (D4h)

  72
• Smart read data (D0h)

  73
• SMART read log sector (D5h)

  75
• SMART return status (DAh)

  75
• SMART save attribution value (D3h)

  75
• SMART write log sector (D6h)

  75
• 6.4.25 Standby (96h, E2h)

  76
• 6.4.26 Standby Immediate (94h, E0h)

  76
• 6.4.27 Write Buffer (E8h)

  76
• 6.4.28 Write Long (32h:with retry, 33h:without retry)

  76
• 6.4.29 Write DMA (CAh)

  76
• 6.4.30 Write Multiple Command (C5h)

  77
• 6.4.31 Write Sector(s) (30h:with retry, 31h:without retry)

  77
• PROGRAMMING REQUIREMENTS

  79
• Reset Response

  79
• Error Posting

  79
• Power Conditions

  81
• Sleep mode

  81
• Standby mode

  81
• Idle mode

  81
• Normal mode

  82
• PROTOCOL OVERVIEW

  83
• PIO Data in Commands

  83
• PIO Read Command

  84
• PIO Read Aborted Command

  84
• PIO Data Out Commands

  84
• PIO Write Command

  85
• PIO Write Aborted Command

  85
• Non-Data Commands

  86
• DMA Data Transfer Commands

  87
• Normal DMA transfer

  88
• Aborted DMA transfer

  88
• Aborted DMA Command

  88
• TIMING

  89
• Register transfers

  89
• PIO data transfers

  91
• Multiword DMA data transfer

  94
• Ultra DMA data transfer

  96
• Initiating an Ultra DMA data in burst

  96
• Ultra DMA data burst timing requirements

  97
• Sustained Ultra DMA data in burst

  98
• Host pausing an Ultra DMA data in burst

  99
• Device terminating an Ultra DMA data in burst

  100
• Host terminating an Ultra DMA data in burst

  101
• Initiating an Ultra DMA data out burst

  102
• Sustained Ultra DMA data out burst

  103
• Device pausing an Ultra DMA data out burst

  104
• Host terminating an Ultra DMA data out burst

  105
• Device terminating an Ultra DMA data out burst

  106
• MAINTENANCE

  107
• GENERAL INFORMATION

  107
• MAINTENANCE PRECAUTIONS

  107
• SERVICE AND REPAIR

  107
• Table 3-1 Specifications

  6
• Table 3-2 Physical Specifications

  7
• Table 3-3 Logical Configurations

  7
• Table 3-4 Performance Specifications

  8
• Table 3-5 Power Requirements

  9
• Table 3-6 Environmental Specifications

  10
• Table 3-6 Environmental Specifications (continued)

  11
• Table 3-7 Reliability Specifications

  11
• Table 4-1 Power Connector Pin Assignment

  16
• Table 4-2 Logical Drive Parameters

  21
• Table 6-1 AT-Bus Interface Signals

  43
• Table 6-2 Interface Signals Description

  45
• Table 6-3 I/O Port Function/Selection Address

  48
• Table 6-4 Command Codes and Parameters

  54
• Table 6-5 Diagnostic Codes

  57
• Table 6-6 IDENTIFY DEVICE information

  58
• Table 6-7 Automatic Standby Timer Periods

  62
• Table 6-8 Set Feature Register Definitions

  67
• Table 6-9 Transfer mode values

  67
• Table 6-10 SMART Feature register values

  71
• Table 6-11 Device SMART data structure

  73
• Table 6-12 Off-line data collection status values

  74
• Table 6-13 Command Errors

  80
• Table 6-14 Power Saving Mode

  81
• Table 6-15 Power Conditions

  82
• Table 6-16 Register transfer to/from device

  91
• Table 6-17 PIO data transfer to/from device

  93
• Table 6-18 Multiword DMA data transfer

  95
• Table 6-19 Ultra DMA data burst timing requirements

  97
• Figure 4-1 Mechanical Dimension

  12
• Figure 4-2 Mounting Dimensions (in Millimeters)

  14
• Figure 4-3 Mounting-Screw Clearance

  15
• Figure 4-4 DC Power Connector, Configuration Jumper Block & AT-Bus Interface Connector (JHST)

  17
• Figure 4-5 Jumper Pin Locations on the Drive PCBA

  19
• Figure 4-6 Options for Jumper Block Configuration

  19
• Figure 4-7 DC Power Connector and AT-Bus Interface Cable Connections

  20
• Figure 5-1 Exploded Mechanical View

  24
• Figure 5-2 SID2001 AT Controller Block Diagram

  27
• Figure 5-3 Read/Write 88C5200

  33
• Figure 6-1 Register transfer to/from device

  90
• Figure 6-2 PIO data transfer to/from device

  92
• Figure 6-3 Multiword DMA data transfer

  94
• Figure 6-4 Initiating an Ultra DMA data in burst

  96
• Figure 6-5 Sustained Ultra DMA data in burst

  98
• Figure 6-6 Host pausing an Ultra DMA data in burst

  99
• Figure 6-7 Device terminating an Ultra DMA data in burst

  100
• Figure 6-8 Host terminating an Ultra DMA data in burst

  101
• Figure 6-9 Initiating an Ultra DMA data out burst

  102
• Figure 6-10 Sustained Ultra DMA data out burst

  103
• Figure 6-11 Device pausing an Ultra DMA data out burst

  104
• Figure 6-12 Host terminating an Ultra DMA data out burst

  105
• Figure 6-13 Device terminating an Ultra DMA data out burst

  106