Инструкции для SMSC flexpwr lan8720

Содержание

• Chapter 1 Introduction

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  • 1.1 General Terms and Conventions

    9
  • 1.2 General Description

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    • Figure 1.1 LAN8720/LAN8720i System Block Diagram

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  • 1.3 Architectural Overview

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    • 1.3.1 Configuration

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      • Figure 1.2 LAN8720/LAN8720i Architectural Overview

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• Chapter 2 Pin Configuration

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  • 2.1 Package Pin-out Diagram and Signal Table

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    • Figure 2.1 LAN8720/LAN8720i 24-QFN Pin Assignments (TOP VIEW)

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    • Table 2.1 LAN8720/LAN8720i 24-PIN QFN Pinout

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• Chapter 3 Pin Description

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  • Table 3.1 Buffer Types

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  • 3.1 MAC Interface Signals

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    • Table 3.2 RMII Signals 24-QFN

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  • 3.2 LED Signals

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    • Table 3.3 LED Signals 24-QFN

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  • 3.3 Management Signals

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    • Table 3.4 Management Signals 24-QFN

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  • 3.4 General Signals

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    • Table 3.5 General Signals 24-QFN

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  • 3.5 10/100 Line Interface Signals

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    • Table 3.6 10/100 Line Interface Signals 24-QFN

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  • 3.6 Analog Reference

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    • Table 3.7 Analog References 24-QFN

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  • 3.7 Power Signals

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    • Table 3.8 Power Signals 24-QFN

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• Chapter 4 Architecture Details

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  • 4.1 Top Level Functional Architecture

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    • Figure 4.1 100Base-TX Data Path

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  • 4.2 100Base-TX Transmit

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    • 4.2.1 100M Transmit Data Across the MII/RMII Interface

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    • 4.2.2 4B/5B Encoding

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      • Table 4.1 4B/5B Code Table

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    • 4.2.3 Scrambling

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    • 4.2.4 NRZI and MLT3 Encoding

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    • 4.2.5 100M Transmit Driver

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    • 4.2.6 100M Phase Lock Loop (PLL)

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      • Figure 4.2 Receive Data Path

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  • 4.3 100Base-TX Receive

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    • 4.3.1 100M Receive Input

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    • 4.3.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery

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    • 4.3.3 NRZI and MLT-3 Decoding

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    • 4.3.4 Descrambling

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    • 4.3.5 Alignment

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    • 4.3.6 5B/4B Decoding

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    • 4.3.7 Receive Data Valid Signal

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      • Figure 4.3 Relationship Between Received Data and Specific MII Signals

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    • 4.3.8 Receiver Errors

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    • 4.3.9 100M Receive Data Across the MII/RMII Interface

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  • 4.4 10Base-T Transmit

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    • 4.4.1 10M Transmit Data Across the MII/RMII Interface

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    • 4.4.2 Manchester Encoding

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    • 4.4.3 10M Transmit Drivers

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  • 4.5 10Base-T Receive

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    • 4.5.1 10M Receive Input and Squelch

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    • 4.5.2 Manchester Decoding

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    • 4.5.3 10M Receive Data Across the MII/RMII Interface

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    • 4.5.4 Jabber Detection

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  • 4.6 MAC Interface

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    • 4.6.1 RMII

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  • 4.7 Reference Clock

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    • Table 4.2 REFCLK Modes

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    • 4.7.1 REF_CLK In Mode

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      • Figure 4.4 External 50MHz clock sources the REF_CLK

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    • 4.7.2 REF_CLK OUT Mode

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      • Figure 4.5 LAN8720 sources REF_CLK from a 25MHz crystal

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      • Figure 4.6 LAN8720 Sources REF_CLK from External 25MHz Source

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  • 4.8 Auto-negotiation

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    • 4.8.1 Parallel Detection

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    • 4.8.2 Re-starting Auto-negotiation

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    • 4.8.3 Disabling Auto-negotiation

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    • 4.8.4 Half vs. Full Duplex

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  • 4.9 HP Auto-MDIX Support

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    • Figure 4.7 Direct Cable Connection vs. Cross-over Cable Connection

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  • 4.10 nINTSEL Strapping and LED Polarity Selection

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    • Table 4.3 LED2/nINTSEL Configuration

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    • Figure 4.8 nINTSEL Strapping on LED2

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  • 4.11 REGOFF and LED Polarity Selection

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    • Figure 4.9 REGOFF Configuration on LED1

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  • 4.12 PHY Address Strapping

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  • 4.13 Variable Voltage I/O

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  • 4.14 Transceiver Management Control

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    • 4.14.1 Serial Management Interface (SMI)

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      • Figure 4.10 MDIO Timing and Frame Structure - READ Cycle

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      • Figure 4.11 MDIO Timing and Frame Structure - WRITE Cycle

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• Chapter 5 SMI Register Mapping

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  • Table 5.1 Control Register: Register 0 (Basic)

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  • Table 5.2 Status Register: Register 1 (Basic)

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  • Table 5.3 PHY ID 1 Register: Register 2 (Extended)

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  • Table 5.4 PHY ID 2 Register: Register 3 (Extended)

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  • Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)

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  • Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)

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  • Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)

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  • Table 5.8 Register 15 (Extended)

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  • Table 5.9 Silicon Revision Register 16: Vendor-Specific

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  • Table 5.10 Mode Control/ Status Register 17: Vendor-Specific

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  • Table 5.11 Special Modes Register 18: Vendor-Specific

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  • Table 5.12 Register 24: Vendor-Specific

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  • Table 5.13 Register 25: Vendor-Specific

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  • Table 5.14 Symbol Error Counter Register 26: Vendor-Specific

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  • Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific

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  • Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific

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  • Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific

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  • Table 5.18 Interrupt Mask Register 30: Vendor-Specific

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  • Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific

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  • Table 5.20 SMI Register Mapping

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  • 5.1 SMI Register Format

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    • Table 5.21 Register 0 - Basic Control

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    • Table 5.22 Register 1 - Basic Status

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    • Table 5.23 Register 2 - PHY Identifier 1

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    • Table 5.24 Register 3 - PHY Identifier 2

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    • Table 5.25 Register 4 - Auto Negotiation Advertisement

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    • Table 5.26 Register 5 - Auto Negotiation Link Partner Ability

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    • Table 5.27 Register 6 - Auto Negotiation Expansion

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    • Table 5.28 Register 16 - Silicon Revision

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    • Table 5.29 Register 17 - Mode Control/Status

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    • Table 5.30 Register 18 - Special Modes

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    • Table 5.31 Register 26 - Symbol Error Counter

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    • Table 5.32 Register 27 - Special Control/Status Indications

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    • Table 5.33 Register 28 - Special Internal Testability Controls

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    • Table 5.34 Register 29 - Interrupt Source Flags

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    • Table 5.35 Register 30 - Interrupt Mask

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    • Table 5.36 Register 31 - PHY Special Control/Status

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  • 5.2 Interrupt Management

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    • 5.2.1 Primary Interrupt System

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      • Table 5.37 Interrupt Management Table

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    • 5.2.2 Alternate Interrupt System

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      • Table 5.38 Alternative Interrupt System Management Table

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  • 5.3 Miscellaneous Functions

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    • 5.3.1 Carrier Sense

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    • 5.3.2 Collision Detect

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    • 5.3.3 Isolate Mode

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    • 5.3.4 Link Integrity Test

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    • 5.3.5 Power-Down modes

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    • 5.3.6 Reset

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    • 5.3.7 LED Description

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    • 5.3.8 Loopback Operation

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      • Figure 5.1 Near-end Loopback Block Diagram

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      • Figure 5.2 Far Loopback Block Diagram

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      • Figure 5.3 Connector Loopback Block Diagram

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    • 5.3.9 Configuration Signals

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      • Table 5.39 MODE[2:0] Bus

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      • Table 5.40 Pin Names for Mode Bits

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• Chapter 6 AC Electrical Characteristics

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  • 6.1 Serial Management Interface (SMI) Timing

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    • Figure 6.1 SMI Timing Diagram

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    • Table 6.1 SMI Timing Values

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  • 6.2 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN)

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    • 6.2.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN)

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      • Figure 6.2 100M RMII Receive Timing Diagram (50MHz REF_CLK IN)

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      • Table 6.2 100M RMII Receive Timing Values (50MHz REF_CLK IN)

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      • Figure 6.3 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN)

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      • Table 6.3 100M RMII Transmit Timing Values (50MHz REF_CLK IN)

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    • 6.2.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK IN)

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      • Figure 6.4 10M RMII Receive Timing Diagram (50MHz REF_CLK IN)

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      • Table 6.4 10M RMII Receive Timing Values (50MHz REF_CLK IN)

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      • Figure 6.5 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN)

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      • Table 6.5 10M RMII Transmit Timing Values (50MHz REF_CLK IN)

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  • 6.3 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK OUT)

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    • 6.3.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK OUT)

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      • Figure 6.6 100M RMII Receive Timing Diagram (50MHz REF_CLK OUT)

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      • Table 6.6 100M RMII Receive Timing Values (50MHz REF_CLK OUT)

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      • Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK OUT)

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      • Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK OUT)

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    • 6.3.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK OUT)

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      • Figure 6.8 10M RMII Receive Timing Diagram (50MHz REF_CLK OUT)

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      • Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK OUT)

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      • Figure 6.9 10M RMII Transmit Timing Diagram (50MHz REF_CLK OUT)

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      • Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK OUT)

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  • 6.4 RMII CLKIN Requirements

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    • Table 6.10 RMII CLKIN (REF_CLK) Timing Values

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  • 6.5 Reset Timing

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    • Figure 6.10 Reset Timing Diagram

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    • Table 6.11 Reset Timing Values

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  • 6.6 Clock Circuit

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    • Table 6.12 LAN8720/LAN8720i Crystal Specifications

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• Chapter 7 DC Electrical Characteristics

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  • 7.1 DC Characteristics

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    • 7.1.1 Maximum Guaranteed Ratings

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      • Table 7.1 Maximum Conditions

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      • Table 7.2 ESD and LATCH-UP Performance

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    • 7.1.2 Operating Conditions

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      • Table 7.3 Recommended Operating Conditions

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    • 7.1.3 Power Consumption

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      • Table 7.4 Power Consumption Device Only (REF_CLK IN MODE)

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      • Table 7.5 Power Consumption Device Only (50MHz REF_CLK OUT MODE)

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    • 7.1.4 DC Characteristics - Input and Output Buffers

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      • Table 7.6 RMII Bus Interface Signals

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      • Table 7.7 LAN Interface Signals

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      • Table 7.8 LED Signals

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      • Table 7.9 Configuration Inputs

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      • Table 7.10 General Signals

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      • Table 7.11 Internal Pull-Up / Pull-Down Configurations

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      • Table 7.12 100Base-TX Transceiver Characteristics

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      • Table 7.13 10BASE-T Transceiver Characteristics

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• Chapter 8 Application Notes

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  • 8.1 Application Diagram

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    • 8.1.1 RMII Diagram

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      • Figure 8.1 Simplified Application Diagram

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    • 8.1.2 Power Supply Diagram

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      • Figure 8.3 High-Level System Diagram for Power

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    • 8.1.3 Twisted-Pair Interface Diagram

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      • Figure 8.5 Copper Interface Diagram

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  • 8.2 Magnetics Selection

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• Chapter 9 Package Outline

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  • Figure 9.1 LAN8720/LAN8720i-EZK 24-QFN Package Outline, 4 x 4 x 0.9 mm Body (Lead-Free)

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  • Table 9.1 24 Terminal QFN Package Parameters

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  • Figure 9.1 QFN, 4x4 Taping Dimensions and Part Orientation

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  • Figure 9.2 Reel Dimensions

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• Chapter 10 Revision History

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  • Table 10.1 Customer Revision History

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