Техническая Спецификация (STM32L152C-DISCO)СодержаниеTable 1. Device summary11 System requirements22 Development toolchain23 Demonstration software24 Revision history2Table 2. Document revision history2Размер: 217,2 КБСтраницы: 3Язык: EnglishПросмотреть
Техническая Спецификация (STM32L152C-DISCO)СодержаниеTable 1. Device summary11 Introduction82 Description92.1 Device overview10Table 2. Ultralow power STM32L15xxC device features and peripheral counts102.2 Ultra-low-power device continuum112.2.1 Performance112.2.2 Shared peripherals112.2.3 Common system strategy112.2.4 Features113 Functional overview12Figure 1. Ultra-low-power STM32L15xxC block diagram123.1 Low power modes13Table 3. Functionalities depending on the operating power supply range14Table 4. CPU frequency range depending on dynamic voltage scaling15Table 5. Functionalities depending on the working mode (from Run/active down to standby)163.2 ARM Cortex-M3 core with MPU173.3 Reset and supply management183.3.1 Power supply schemes183.3.2 Power supply supervisor183.3.3 Voltage regulator193.3.4 Boot modes193.4 Clock management20Figure 2. Clock tree213.5 Low power real-time clock and backup registers223.6 GPIOs (general-purpose inputs/outputs)223.7 Memories233.8 DMA (direct memory access)233.9 LCD (liquid crystal display)24Table 6. VLCD rail decoupling243.10 ADC (analog-to-digital converter)243.10.1 Temperature sensor253.10.2 Internal voltage reference (VREFINT)253.11 DAC (digital-to-analog converter)253.12 Operational amplifier263.13 Ultra-low-power comparators and reference voltage263.14 System configuration controller and routing interface263.15 Touch sensing263.16 Timers and watchdogs27Table 7. Timer feature comparison273.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11)273.16.2 Basic timers (TIM6 and TIM7)283.16.3 SysTick timer283.16.4 Independent watchdog (IWDG)283.16.5 Window watchdog (WWDG)283.17 Communication interfaces283.17.1 I²C bus283.17.2 Universal synchronous/asynchronous receiver transmitter (USART)293.17.3 Serial peripheral interface (SPI)293.17.4 Inter-integrated sound (I2S)293.17.5 Universal serial bus (USB)293.18 CRC (cyclic redundancy check) calculation unit293.19 Development support304 Pin descriptions31Figure 3. STM32L15xVC UFBGA100 ballout31Figure 4. STM32L15xVC LQFP100 pinout32Figure 5. STM32L15xRC LQFP64 pinout33Figure 6. STM32L15xUC WLCSP63 ballout34Figure 7. STM32L15xCC UFQFPN48 pinout35Figure 8. STM32L15xCC LQFP48 pinout36Table 8. Legend/abbreviations used in the pinout table37Table 9. STM32L15xxC pin definitions (continued)38Table 10. Alternate function input/output (continued)455 Memory mapping51Figure 9. Memory map516 Electrical characteristics526.1 Parameter conditions526.1.1 Minimum and maximum values526.1.2 Typical values526.1.3 Typical curves526.1.4 Loading capacitor526.1.5 Pin input voltage52Figure 10. Pin loading conditions52Figure 11. Pin input voltage526.1.6 Power supply scheme53Figure 12. Power supply scheme536.1.7 Optional LCD power supply scheme54Figure 13. Optional LCD power supply scheme546.1.8 Current consumption measurement54Figure 14. Current consumption measurement scheme546.2 Absolute maximum ratings55Table 11. Voltage characteristics55Table 12. Current characteristics55Table 13. Thermal characteristics566.3 Operating conditions566.3.1 General operating conditions56Table 14. General operating conditions566.3.2 Embedded reset and power control block characteristics57Table 15. Embedded reset and power control block characteristics576.3.3 Embedded internal reference voltage59Table 16. Embedded internal reference voltage calibration values59Table 17. Embedded internal reference voltage596.3.4 Supply current characteristics61Table 18. Current consumption in Run mode, code with data processing running from Flash61Table 19. Current consumption in Run mode, code with data processing running from RAM62Table 20. Current consumption in Sleep mode63Table 21. Current consumption in Low power run mode64Table 22. Current consumption in Low power sleep mode65Table 23. Typical and maximum current consumptions in Stop mode66Table 24. Typical and maximum current consumptions in Standby mode67Table 25. Peripheral current consumption686.3.5 Wakeup time from low-power mode70Table 26. Low power mode wakeup timings706.3.6 External clock source characteristics71Table 27. High-speed external user clock characteristics72Figure 15. High-speed external clock source AC timing diagram72Table 28. Low-speed external user clock characteristics73Figure 16. Low-speed external clock source AC timing diagram73Table 29. HSE oscillator characteristics74Figure 17. HSE oscillator circuit diagram75Table 30. LSE oscillator characteristics (fLSE = 32.768 kHz)75Figure 18. Typical application with a 32.768 kHz crystal766.3.7 Internal clock source characteristics77Table 31. HSI oscillator characteristics77Table 32. LSI oscillator characteristics77Table 33. MSI oscillator characteristics786.3.8 PLL characteristics80Table 34. PLL characteristics806.3.9 Memory characteristics80Table 35. RAM and hardware registers80Table 36. Flash memory and data EEPROM characteristics81Table 37. Flash memory and data EEPROM endurance and retention816.3.10 EMC characteristics82Table 38. EMS characteristics82Table 39. EMI characteristics836.3.11 Electrical sensitivity characteristics83Table 40. ESD absolute maximum ratings83Table 41. Electrical sensitivities846.3.12 I/O current injection characteristics84Table 42. I/O current injection susceptibility846.3.13 I/O port characteristics85Table 43. I/O static characteristics85Table 44. Output voltage characteristics86Table 45. I/O AC characteristics87Figure 19. I/O AC characteristics definition886.3.14 NRST pin characteristics88Table 46. NRST pin characteristics88Figure 20. Recommended NRST pin protection896.3.15 TIM timer characteristics89Table 47. TIMx characteristics896.3.16 Communications interfaces90Table 48. I2C characteristics90Figure 21. I2C bus AC waveforms and measurement circuit91Table 49. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)91Table 50. SPI characteristics92Figure 22. SPI timing diagram - slave mode and CPHA = 093Figure 23. SPI timing diagram - slave mode and CPHA = 1(1)93Figure 24. SPI timing diagram - master mode(1)94Table 51. I2S characteristics94Figure 25. I2S slave timing diagram (Philips protocol)(1)96Figure 26. I2S master timing diagram (Philips protocol)(1)96Table 52. USB startup time97Table 53. USB DC electrical characteristics97Figure 27. USB timings: definition of data signal rise and fall time98Table 54. USB: full speed electrical characteristics986.3.17 12-bit ADC characteristics99Table 55. ADC clock frequency99Table 56. ADC characteristics99Table 57. ADC accuracy101Figure 28. ADC accuracy characteristics102Figure 29. Typical connection diagram using the ADC102Figure 30. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion103Table 58. RAIN max for fADC = 16 MHz103Figure 31. Power supply and reference decoupling (VREF+ not connected to VDDA)104Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA)1046.3.18 DAC electrical specifications105Table 59. DAC characteristics105Figure 33. 12-bit buffered /non-buffered DAC1076.3.19 Operational amplifier characteristics107Table 60. Operational amplifier characteristics1076.3.20 Temperature sensor characteristics109Table 61. Temperature sensor calibration values109Table 62. Temperature sensor characteristics1096.3.21 Comparator109Table 63. Comparator 1 characteristics (continued)109Table 64. Comparator 2 characteristics1106.3.22 LCD controller111Table 65. LCD controller characteristics1117 Package characteristics1127.1 Package mechanical data112Figure 34. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline112Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data113Figure 35. LQFP100 recommended footprint113Figure 36. LQFP100 package top view114Figure 37. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline115Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data116Figure 38. LQFP64 recommended footprint116Figure 39. LQFP64 package top view117Figure 40. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline118Table 68. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data119Figure 41. LQFP48 recommended footprint119Figure 42. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline120Table 69. UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm pitch package mechanical data121Figure 43. UFQFPN48 recommended footprint121Figure 44. UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package outline122Table 70. UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package mechanical data122Figure 45. WLCSP63, 0.400 mm pitch wafer level chip size package outline123Table 71. WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data1247.2 Thermal characteristics125Table 72. Thermal characteristics125Figure 46. Thermal resistance1267.2.1 Reference document1268 Part numbering127Table 73. STM32L15xxC ordering information scheme1279 Revision History128Table 74. Document revision history (continued)128Размер: 2,1 МБСтраницы: 132Язык: EnglishПросмотреть
