Sony DFW-X700 用户手册

DFW-SX900
DFW-X700

This chapter describes CSR addresses using the lower 32 bits of 64 bits. (CSR: Abbreviation of Control and Status Register)

The omitted upper 32 bits are 

∗∗∗∗

FFFFh. (

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 changes according to the connection of the IEEE1394 Serial Bus.)

 Read/Write of the CSR is executed in units of Quadlet (4 bytes). The CSR address is the address of the leading byte of the

Quadlet.

 When describing the 32-bit command set for CSR in Hex, bit 0 is described as MSB (Most Significant Bit).

Example :

82012345h = 10000010

00000001

00100011

01000101b

:

:

bit 0

bit 31

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Executes the same operations as when Factory Setup was selected in Current Memory Channel of CSR F0F00624h.

Command: 80000000h

Resets the CSR F0F00800hth functions to factory settings.

At this time, return the CSR F0F00624h Current Mem. ch also to “0”.

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

CSR F0F00600h to F0F00624h control isochronous image transmission, and load/save settings of the camera.

Specify the Frame Rates 1 to 3.

Frame Rate

Command

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1 (3.75 fps)

20000000h

2 (7.5 fps)

40000000h

3 (15 fps)

60000000h