Motorola 24-Bit Digital Signal Processor 用户手册
OVERVIEW AND DATA ALU ARCHITECTURE
MOTOROLA
DATA ARITHMETIC LOGIC UNIT
3 - 5
3.2.1 Data ALU Input Registers (X1, X0, Y1, Y0)
X1, X0, Y1, and Y0 are four 24-bit, general-purpose data registers. They can be treated
as four independent, 24-bit registers or as two 48-bit registers called X and Y, developed
by concatenating X1:X0 and Y1:Y0, respectively. X1 is the most significant word in X and
Y1 is the most significant word in Y. The registers serve as input buffer registers between
the XDB or YDB and the MAC unit. They act as Data ALU source operands and allow
new operands to be loaded for the next instruction while the current instruction uses the
as four independent, 24-bit registers or as two 48-bit registers called X and Y, developed
by concatenating X1:X0 and Y1:Y0, respectively. X1 is the most significant word in X and
Y1 is the most significant word in Y. The registers serve as input buffer registers between
the XDB or YDB and the MAC unit. They act as Data ALU source operands and allow
new operands to be loaded for the next instruction while the current instruction uses the
56
24
24
56
56
56
56
X DATA BUS
Y DATA BUS
24
24
X0
X1
Y0
Y1
24
24
MULTIPLIER
ACCUMULATOR,
ROUNDING,
AND LOGIC UNIT
SHIFTER
A (56)
B (56)
SHIFTER/LIMITER
Figure 3-2 Data ALU