Epson S1D13708 用户手册
Epson Research and Development
Page 11
Vancouver Design Center
Interfacing to 8-bit Processors
S1D13708
Issue Date: 01/11/25
X39A-G-015-01
4 8-Bit Processor to S1D13708 Interface
4.1 Hardware Connections
The interface between the S1D13708 and an 8-bit processor requires minimal glue logic. A
decoder is used to generate the chip select for the S1D13708 based on where the S1D13708
is mapped into memory. Alternatively, if the processor supports a chip select module, it can
be programmed to generate a chip select for the S1D13708 without the need of an address
decoder.
decoder is used to generate the chip select for the S1D13708 based on where the S1D13708
is mapped into memory. Alternatively, if the processor supports a chip select module, it can
be programmed to generate a chip select for the S1D13708 without the need of an address
decoder.
An inverter inverts A0 to generate the BHE# signal for the S1D13708. BS# (bus start) and
RD/WR# are not used by the Generic #2 Host Bus Interface and must be tied high
(connected to IO V
RD/WR# are not used by the Generic #2 Host Bus Interface and must be tied high
(connected to IO V
DD
).
In order to support an 8-bit processor with a 16-bit peripheral, the low and high order bytes
of the data bus must be connected together. The following diagram shows a typical imple-
mentation of an 8-bit processor to S1D13708 interface.
of the data bus must be connected together. The following diagram shows a typical imple-
mentation of an 8-bit processor to S1D13708 interface.
Figure 4-1: Typical Implementation of 8-bit Processor to S1D13708 Interface
Generic 8-bit Bus
S1D13708
A[16:0]
D[7:0]
Decoder
WAIT#
WE#
RD#
A0
BUSCLK
AB[15:0]
DB[7:0]
CS#
WAIT#
WE#
RD#
RD/WR#
CLKI
RESET#
DB[15:8]
BS#
BHE#
System RESET
Note:
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
IO V
DD
A17
M/R#