Renesas rl78 用户手册
RL78/G1A
CHAPTER 13 SERIAL INTERFACE IICA
Figure 13-1. Block Diagram of Serial Interface IICA
IICE0
D Q
DFC0
SDAA0/
P61
SCLA0/
P60
INTIICA0
IICCTL00.STT0, SPT0
IICCTL01.PRS0
IICS0.MSTS0, EXC0, COI0
IICS0.MSTS0, EXC0, COI0
f
CLK
f
CLK
/2
LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
STCF0 IICBSY0 STCEN0 IICRSV0
WUP0
CLD0
DAD0
DFC0 PRS0
SMC0
PM60
Internal bus
IICA status register 0 (IICS0)
IICA control register 00
(IICCTL00)
Slave address
register 0 (SVA0)
Noise
eliminator
Match
signal
Match signal
IICA shift
register 0 (IICA0)
SO latch
Set
Clear
IICWL0
TRC0
DFC0
Data hold
time correction
circuit
Start
condition
generator
Stop
condition
generator
ACK
generator
Wakeup
controller
N-ch open-
drain output
drain output
PM61
Noise
eliminator
Bus status
detector
ACK detector
Stop condition
detector
Serial clock
counter
Interrupt request
signal generator
Serial clock
controller
Serial clock
wait controller
Start condition
detector
Internal bus
IICA flag register 0
(IICF0)
(IICF0)
IICA control register 01
(IICCTL01)
(IICCTL01)
N-ch open-
drain output
drain output
Output
latch
(P60)
(P60)
Output
latch
(P61)
(P61)
WUP0
Sub-circuit
for standby
Filter
Filter
Output control
IICA shift register 0 (IICA0)
Counter
IICA low-level width
setting register 0 (IICWL0)
IICA high-level width
setting register 0 (IICWH0)
Selector
f
MCK
R01UH0305EJ0200 Rev.2.00
567
Jul 04, 2013