Intel 315889-002 用户手册

315889-002

31

The VID_Select, LL1 and LL0 control signal form a 3-bit load line selection and will used 
to configure the VRM/EVRD to supply the proper load line for the processors. These 
signals are programmed by the CPU package pin bonding. The VID_Select control 
signal will select the appropriate VR10 or VR11 VID table and remap the VID [6:0] pins 
to the appropriate DAC input. The signals are open-collector/drain or equivalent 
signals. 

 shows the VID_Select, LL1, and LL0 pins specification and 

shows equations in how to obtain V

MAX

 and V

MIN

 based on LL0, LL1, and VID_Select bit 

code. For VRMs a set of additional signals extent the usability of a modular solution, 
refer to 

.

It is EXPECTED that the pull-up resistors for LL0 and LL1 will be located on the 
baseboard and will not be integrated into the VRM. However, the pull-up resistor for 
VID_Select should be located on the VRM and to maintain backward compatibility to 
VRM 10.2 compliant platforms a pull-down resistor of 10 k

Ω 

is also required. The pull-

down resistor is required for VRMs only and not required for EVRDs. Typically, for EVRD 
converters, this signal will be pulled up to VTT (1.1 V/1.2 V) via a 4.7 k

Ω

 resistor. As an 

option, 3.3 V with ± 5% regulation tolerance, may be used instead of VTT for VRM or 
EVRD converters. Pull-ups to 12 V or 5 V are not supported by the CPU package.

The VR 10 and VR 11.0 VID pins do not have the same voltage weight. See 

 

for the VID bit mapping.

I

OL

Output Low Current

0

4

mA

V

IH

Input Voltage High

0.8

3.465

V

V

IL

Input Voltage Low

0

0.4

V

VR 10.x

-

VID 4

VID 3

VID 2

VID 1

VID 0

VID 5

VID 6

bit 

weight

800mV

400mV

200mV

100mV

50mV

25mV

12.5mV

6.25mV

VR 11.0

VID 7

VID 6

VID 5

VID 4

VID 3

VID 2

VID 1

VID 0