Renesas SH7709S 用户手册
Rev. 5.00, 09/03, page 379 of 760
Bit 6—Reserved: This bit can be read or written. The wite value should always be 0.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the clock input to CMCNT from
among the four internal clocks obtained by dividing the system clock (P
among the four internal clocks obtained by dividing the system clock (P
φ
). When the STR bit in
CMSTR is set to 1, CMCNT0 begins incrementing on the clock selected by CKS1 and CKS0.
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
P
φ
/4 (Initial
value)
1
P
φ
/8
1
0
P
φ
/16
1
P
φ
/64
Compare Match Counter 0 (CMCNT0)
Compare match counter 0 (CMCNT0) is a 16-bit register used as an up-counter.
When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the
STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on that clock. When the CMCNT0
value matches that of compare match constant register 0 (CMCOR0), CMCNT0 is cleared to
H'0000 and the CMF flag in CMCSR0 is set to 1.
STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on that clock. When the CMCNT0
value matches that of compare match constant register 0 (CMCOR0), CMCNT0 is cleared to
H'0000 and the CMF flag in CMCSR0 is set to 1.
CMCNT0 is initialized to H'0000 by a reset, but retains its previous value in standby mode.
Bit:
15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W