Sanyo EP93F 用户手册

LC723780

LC72336/LC72338

XIN

XOUT

FMIN

AMIN

DATA

LATCH

DATA

LATCH

BUS

DRIVR.

DATA

LATCH

SIO

BUS

DRIVR.

BUS

DRIVR.

BUS

DRIVR.

BUS

DRIVR.

PJ3

PKO/INT

INTERRUPT

PK1/INT

PK2/INT

PJ2

PJ1

PJ0

DATA

LATCH

PK3/INT

ADI4/PI0

ADI5/PI1

ADI6/PI2

ADI7/PI3

PL3

PL2

PL1

PL0

BUS

DRIVR.

DATA

LATCH

PM3

PM2

PM1

PM0

BUS

DRIVR.

DATA

LATCH

PO3

PO2

PO1

PO0

BUS

DRIVR.

DATA

LATCH

PP3

PP2

PP1

PP0

BUS

DRIVR.

DATA

LATCH

PQ3

PQ2

PQ1

PQ0

BUS

DRIVR.

DATA

LATCH

PR3

PR2

PR1

PR0

BUS

DRIVR.

DATA

LATCH

PS3

PS2

PT1

PT0

PS1

PS0

BUS

DRIVR.

DATA

LATCH

BUS

DRIVR.

INE0

SUBPD

EO1

EO2

DATA

LATCH

BUS

DRIVR.

DATA

LATCH

BUS

DRIVR.

BEEP GEN

(PRG/FIX)

PN3

PN2

PN1

PN0/BEEP

MPX

SELECTOR

PHASE

DETECTOR

SUB

C.P.

UNLOCK

F/F

REFERENCE DIVIDER

DIVIDER

SYSTEM CLOCK

GENERATOR

1/16,1/17

PROGRAMMBLE DIVIDER

1/2

PLL DATA LATCH

UNIVERSAL COUNTER

(20bits)

SNSF/F

SNS

DTR/ADR

RAM

ROM

16k 4bits

64k 16bits

ADDRESS

DECODER

BANK

TIMER

PROG 2

FIX 2

ADDRESS DECODER

PROGRAM COUNTER

BUS

CONTROL

INSTRUCTION

DECODER

STACK 32k 16bits

(PC,BANK,CF,PF)

SKIP

JUDGE

LATCH

ALU

BUS

STATUS

READ

STATUS WRITE

A/D-C (8bits)

INTERRUPT

CONTROL

DATA

LATCH

BUS

DRIVR.

DATA

LATCH

BUS

DRIVR.

DATA

LATCH

BUS

DRIVR.

DATA

LATCH

BUS

DRIVR.

DATA

LATCH

BUS

DRIVR.

MPX(8ch)

ADI0/PH0

SI0/PG3

SO0/PG2

SCK0/PG1

PG0

SI1/PF3

SO1/PF2

SCK1/PF1

SI2/PE3

SO2/PE2

SCK2/PE1

PF0

PE0

INT4/PD0

PD2

PD3

PC3

PC2

PC1

PC0

INT5/PD1

ADI1/PH1

ADI2/PH2

ADI3/PH3

PA0

RESET

LCTR

PA1

PA2

PA3

PB0

PB1

PB2

PB3

HOLD

TEST1

TEST2

HCTR

VSS

VDD

SNS

VDET

XIN

XOUT

FMIN

AMIN

SNS

HCTR

LCTR

HOLD

TEST1

TEST2

PA0

PA1

PA2

PA3

PB0

PB1

PB2

PB3

PC0

PC1

PC2

PC3

PG0

EO1 EO2

COM1

SCK0 / PG1

SO0 / PG2

SI0 / PG3

COM2 COM2

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16

S17 / PE0

S18 / PE1 / SCK2

S19 / PE2 / SO2

S20 / PE3 / SI2

S21 / PF0

S22 / PF1 / SCK1

S23 / PF2 / SO1

S24 / PF3 / SI1

S29 / PN0 / BEEP

S30 / PN1

S31 / PN2

S32 / PN3

PJ3 / DAC3

S25 / PM0

S26 / PM1

S27 / PM2

S28 / PM3

LATCH

BUS

DRIV.

LATCH

BUS

DRIV.

LATCH

BUS

DRIV.

LATCH

BUS

DRIV.

LATCH

BUS

DRIV.

LATCH

BUS

DRIV.

LATCH

BUS

DRIV.

BUS

DRIVER

BEEP

PJ2 / DAC2

PJ1 / DAC1

PJ0 / DAC0

PK3

PK2

PK1 / INT1

PK0 / INT0

PH3 / ADI3

PH2 / ADI2

PH1 / ADI1

PH0 / ADI0

MPX

INTERRUPT

LCD

PORT

DRIVER

LATCH

LCPA / B

SEG

PLA

PHASE

DETECTOR

UNLOCK

F / F

COMMON

DRIVER

SELECTOR

REFERENCE DIVIDER

PROGRAMMABLE DIVIDER

LATCH

DIVIDER

1 /16, 1 /17

SNSFF

V-DET

1 /2

UNIVERSAL

COUNTER

(20bits)

RAM

512 X 4bits

ROM

8k X 16bits

LC72336

6k X 16bits

ADDRESS

DECODER

BUS

DRIV.

LATCH

BUS

DRIV.

LATCH

BUS

DRIV.

SIO

LATCH

BUS

DRIV.

ADC

DAC

JUDGE

ALU

STACK

PROGRAM

COUNTER

INSTRU-

CTION

DECODER

ADDRESS

DECODER

∗

MPX

Car Audio

Overview

Functions

Overview

Functions

Block Diagram

Electronic Tuning ETR Controllers

The LC72336 and LC72338 are system-on-chip electronic tuning microcontrollers that integrate both a PLL circuit
that can operate at up to 150 MHz and a 1/3 duty LCD driver. They also feature a highly efficient instruction set
and powerful hardware

■

High-speed programmable divider

■

Program memory (ROM): LC72336 - 6143 words 16 bits (12 KB)

LC72338 - 8191 words 16 bits (16 KB)

■

Data memory (RAM): 512 4 bits

■

All instructions are one word

■

Cycle time: 1.33

■

Stack: 8 levels

■

LCD driver: Up to 96 segments (1/3 duty, 1/3 bias)

■

Serial I/O: Up to 3 channels (8-bit 3-wire type)

■

External interrupt: Two channels (INT0 and INT1)

Supports both rising edge and falling edge detection

■

Package: LC72336 - QIP80E (14 20 mm)

LC72338 - QIP80E (14 20 mm)

■

ROM/RAM: 40 KB/2 KB (LC723781)

48 KB/2 KB (LC723782)
64 KB/4 KB (LC723783)
96 KB/6 KB (LC723784)
128 KB/8 KB (LC723785)

■

Cycle time: 1.33

s/833 ns (all instructions are one word) at 4.5 MHz/7.2 MHz

■

Serial I/O: Three channels (supports 8-bit, 2- or 3-wire systems) MSB/LSB first switching

■

Multiple interrupts: 16 levels

■

A/D converter: 8-bit successive approximation A/D converter with 8 input channels

■

PLL block: Dead zone control, unlocked state detection circuit

■

QTP version: LC72F3781

■

Package: QIP100E (14 20 mm)

The LC723780 series are large-memory ETR controllers that provide up to 128 KB of ROM and up to 8 KB of
RAM.
In addition to a rich set of table reference instructions to take advantage of the large ROM capacity, these devices
also feature an improved interrupt system for direct control of the CD mechanism and the CD DSP, support for
RDS products, and powerful communications for use within the end product and with external systems as well.
In car audio applications in particular, these communication functions allow a reduction in the number connecting
wires between the front panel circuit board and the main system circuit board.

Series