National Instruments 320571-01 用户手册
Introduction to the NI-DSP Analysis VIs
Part 2
Part 2: Introduction to the NI-DSP Analysis VIs
1-6
NI-DSP SRM for LabVIEW for Windows
The error in/error out cluster contains the following elements:
The boolean value is true if an error occurred, false if no error occurred.
code is the error code.
source is the source of the error. If an error occurs during execution, the VI sets source to the name
of the VI that produced the error.
of the VI that produced the error.
Every VI checks error in first. If there is an error, the VI does not execute any DSP code but simply passes the
contents of error in to the error out cluster. If there is no error, the VI executes. One advantage of this error
in/error out design is that you can connect several I/O operations together so that, if an error occurs, subsequent VIs
do not perform undesired actions. DSP Free Memory will execute even if an error occurs. This ensures that
allocated buffers are freed even if an error occurred.
contents of error in to the error out cluster. If there is no error, the VI executes. One advantage of this error
in/error out design is that you can connect several I/O operations together so that, if an error occurs, subsequent VIs
do not perform undesired actions. DSP Free Memory will execute even if an error occurs. This ensures that
allocated buffers are freed even if an error occurred.
Another advantage of this error in/error out design is that you can establish the order of a set of operations, even if
there is no other data flow between the operations. Connecting the error out of the first VI to the error in of the
second VI establishes data flow and therefore execution order. You could do the same thing with a Sequence
structure, but with the error in/error out design, you can establish the order with all of the operations at the top level
of the block diagram. For example, in Figure 1-8, you allocate DSP Handle Clusters X and Y as inputs, and you want
to free X and Y after the DSP Add VI has been executed. If you simply connect X to the DSP Free Memory VI as
shown in Figure 1-8, there is no sequential order between the DSP Add VI and the DSP Free Memory VI. If the DSP
Free Memory VI executes first, the DSP Add VI will receive an invalid handle because that DSP Handle Cluster was
deallocated.
there is no other data flow between the operations. Connecting the error out of the first VI to the error in of the
second VI establishes data flow and therefore execution order. You could do the same thing with a Sequence
structure, but with the error in/error out design, you can establish the order with all of the operations at the top level
of the block diagram. For example, in Figure 1-8, you allocate DSP Handle Clusters X and Y as inputs, and you want
to free X and Y after the DSP Add VI has been executed. If you simply connect X to the DSP Free Memory VI as
shown in Figure 1-8, there is no sequential order between the DSP Add VI and the DSP Free Memory VI. If the DSP
Free Memory VI executes first, the DSP Add VI will receive an invalid handle because that DSP Handle Cluster was
deallocated.
Figure 1-8. An Example That Does Not Use error in/error out
for Sequencing VIs
If you connect the VIs as shown Figure 1-9 instead, you ensure that the DSP Add VI executes before the DSP Free
Memory VI.
Memory VI.