Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
Altera Corporation
95
32323232
32-Bit Instruction Set
2
3
2
-B
it In
st
st
ru
ctio
n
n
Se
t
t
STP
Store 32-bit Data To Memory (Pointer Addressing Mode)
Operation:
Not preceded by PFX:
Mem32[align32(RP + (IMM5
× 4))] ← RA
Preceded by PFX:
Mem32[align32(RP + (
σ(K : IMM5) × 4))] ← RA
Assembler Syntax:
STP [%rP,IMM5],%rA
Example:
Not preceded by PFX:
STP [%L2,3],%g3 ; Store %g3 to location [%L2 + 12]
Preceded by PFX:
PFX %hi(102)
STP [%L2,%lo(102)],%g3 ; Store %g3 to
; location [%L2 + 408]
Description:
Not preceded by PFX:
Stores the 32-bit data value in RA to memory. Data is always written to a word-
aligned address given by bits [31..2] of RP (the two LSBs of RP are ignored) plus
aligned address given by bits [31..2] of RP (the two LSBs of RP are ignored) plus
a 5-bit, unsigned, word-scaled offset given by IMM5.
This instruction is similar to ST, but additionally allows a positive 5-bit offset to be
applied to any of four base-pointers in a single instruction. The base-pointer must
applied to any of four base-pointers in a single instruction. The base-pointer must
be one of the four registers: %L0, %L1, %L2, or %L3.
Preceded by PFX:
A 16-bit offset is formed by concatenating the 11-bit K-register with IMM5 (5 bits).
The 16-bit offset (K : IMM5) is sign-extended to 32 bits, multiplied by four, and
added to bits 31..2 of RP to yield a word-aligned effective address.
The 16-bit offset (K : IMM5) is sign-extended to 32 bits, multiplied by four, and
added to bits 31..2 of RP to yield a word-aligned effective address.
Condition Codes:
Flags: Unaffected
Instruction Format:
RPi5
Instruction Fields:
A = Register index of operand RA
IMM5 = 5-bit immediate value
IMM5 = 5-bit immediate value
P = Index of base-pointer register, less 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0
P
IMM5
A
N
V
Z
C
−
−
−
−