Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
4
Altera Corporation
Overview
The K Register
The K register is an 11-bit prefix value and is always set to 0 by every
instruction except PFX. A PFX instruction sets K directly from the IMM11
instruction field. Register K contains a non-zero value only for an
instruction immediately following PFX.
instruction except PFX. A PFX instruction sets K directly from the IMM11
instruction field. Register K contains a non-zero value only for an
instruction immediately following PFX.
A PFX instruction disables interrupts for one cycle, so the two-instruction
PFX sequence is an atomic CPU operation. Also, PFX sequence instruction
pairs are skipped together by SKP-type conditional instructions.
PFX sequence is an atomic CPU operation. Also, PFX sequence instruction
pairs are skipped together by SKP-type conditional instructions.
The K register is not directly accessed by software, but is used indirectly.
A MOVI instruction, for example, transfers all 11 bits of K into bits 15..5 of
the destination register. This K-reading operation will only yield a non-
zero result when the previous instruction is PFX.
A MOVI instruction, for example, transfers all 11 bits of K into bits 15..5 of
the destination register. This K-reading operation will only yield a non-
zero result when the previous instruction is PFX.
The Program Counter
The program counter (PC) register contains the byte-address of the
currently executing instruction. Since all instructions must be half-word-
aligned, the least-significant bit of the PC value is always 0.
currently executing instruction. Since all instructions must be half-word-
aligned, the least-significant bit of the PC value is always 0.
The PC increments by two (PC
← PC + 2) after every instruction unless the
PC is explicitly set. The following instructions modify PC directly: BR,
BSR, CALL, JMP, LRET, RET and TRET. The PC is 33-bits wide in a 32-bit
Nios CPU and 17-bits wide in a 16-bit Nios CPU.
BSR, CALL, JMP, LRET, RET and TRET. The PC is 33-bits wide in a 32-bit
Nios CPU and 17-bits wide in a 16-bit Nios CPU.
Control Registers
There are five defined control registers that are addressed independently
from the general-purpose registers. The RDCTL and WRCTL instructions
are the only instructions that can read or write to these control registers
(meaning %ctl0 is unrelated to %g0).
from the general-purpose registers. The RDCTL and WRCTL instructions
are the only instructions that can read or write to these control registers
(meaning %ctl0 is unrelated to %g0).
STATUS (%ctl0)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IE
IPRI CWP
N
V
Z
C