Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
Altera Corporation
17
Getting
Overview
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External Hardware Interrupt Sources
An external source can request a hardware interrupt by driving a 6-bit
interrupt number on the Nios CPU irq_number inputs while
simultaneously asserting true (1) the Nios CPU irq input pin. The Nios
CPU will process the indicated exception if the IE bit is true (1) and the
requested interrupt number is smaller than (higher priority than) the
current value in the IPRI field of the STATUS register. Control is
transferred to the exception handler whose number is given by the
irq_number inputs.
interrupt number on the Nios CPU irq_number inputs while
simultaneously asserting true (1) the Nios CPU irq input pin. The Nios
CPU will process the indicated exception if the IE bit is true (1) and the
requested interrupt number is smaller than (higher priority than) the
current value in the IPRI field of the STATUS register. Control is
transferred to the exception handler whose number is given by the
irq_number inputs.
External logic for producing the irq_number input and for driving the irq
input pin is automatically generated by the Nios SOPC builder software
and included in the peripheral bus module PBM outside the CPU. An
interrupt-capable peripheral need only generate one or more interrupt-
request signals that are combined within the PBM to produce the Nios
irq_number and irq inputs.
input pin is automatically generated by the Nios SOPC builder software
and included in the peripheral bus module PBM outside the CPU. An
interrupt-capable peripheral need only generate one or more interrupt-
request signals that are combined within the PBM to produce the Nios
irq_number and irq inputs.
The Nios irq input is level sensitive. The irq and irq_number inputs are
sampled at the rising edge of each clock. External sources that generate
interrupts should assert their irq output signals until the interrupt is
acknowledged by software (e.g. by writing a register inside the
interrupting peripheral to 0). Interrupts that are asserted and then de-
asserted before the Nios CPU core can begin processing the exception are
ignored.
sampled at the rising edge of each clock. External sources that generate
interrupts should assert their irq output signals until the interrupt is
acknowledged by software (e.g. by writing a register inside the
interrupting peripheral to 0). Interrupts that are asserted and then de-
asserted before the Nios CPU core can begin processing the exception are
ignored.
Internal Exception Sources
There are two sources of internal exceptions: register window-overflow
and register window-underflow. The Nios processor architecture allows
precise exception handling for all internally generated exceptions. In each
case, it is possible for the exception handler to fix the exceptional
condition and make it behave as if the exception-generating instruction
had succeeded.
and register window-underflow. The Nios processor architecture allows
precise exception handling for all internally generated exceptions. In each
case, it is possible for the exception handler to fix the exceptional
condition and make it behave as if the exception-generating instruction
had succeeded.
Register Window Underflow
A register window underflow exception occurs whenever the lowest valid
register window is in use (CWP = LO_LIMIT) and a SAVE instruction is
issued. The SAVE instruction moves CWP below LO_LIMIT and %sp is
set per the normal operation of SAVE. A register window underflow
exception is generated, which transfers control to an exception-handling
subroutine before the instruction following SAVE is executed.
register window is in use (CWP = LO_LIMIT) and a SAVE instruction is
issued. The SAVE instruction moves CWP below LO_LIMIT and %sp is
set per the normal operation of SAVE. A register window underflow
exception is generated, which transfers control to an exception-handling
subroutine before the instruction following SAVE is executed.