Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
Altera Corporation
21
Getting
Overview
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Interrupts are automatically disabled upon entry to an exception handler,
so there is no danger of ISTATUS being overwritten by a subsequent
interrupt or exception. The case of nested exception handlers (exception
handlers that use or re-enable exceptions) is discussed in detail below.
Nested exception handlers must explicitly preserve, maintain, and restore
the contents of the ISTATUS register before and after enabling subsequent
interrupts.
so there is no danger of ISTATUS being overwritten by a subsequent
interrupt or exception. The case of nested exception handlers (exception
handlers that use or re-enable exceptions) is discussed in detail below.
Nested exception handlers must explicitly preserve, maintain, and restore
the contents of the ISTATUS register before and after enabling subsequent
interrupts.
Return-Address
When an exception occurs, execution of the interrupted program is
temporarily suspended. The instruction in the interrupted program that
was preempted (i.e., the instruction that would have executed, but did not
yet execute) is taken as the return-location for exception processing.
temporarily suspended. The instruction in the interrupted program that
was preempted (i.e., the instruction that would have executed, but did not
yet execute) is taken as the return-location for exception processing.
The return-location is saved in %o7 (in the exception handler’s newly
opened register window) before control is transferred to the exception
handler. The value stored in %o7 is the byte-address of the return-
instruction right-shifted by one place. This value is suitable directly for
use as the target of a TRET instruction without modification. Exception
handlers will usually execute a TRET %o7 instruction to return control to
the interrupted program.
opened register window) before control is transferred to the exception
handler. The value stored in %o7 is the byte-address of the return-
instruction right-shifted by one place. This value is suitable directly for
use as the target of a TRET instruction without modification. Exception
handlers will usually execute a TRET %o7 instruction to return control to
the interrupted program.
Simple and Complex Exception Handlers
The Nios processor architecture permits efficient, simple exception
handlers. The hardware itself accomplishes much of the status- and
register-preservation overhead required by an exception handler. Simple
exception handlers can substantially ignore all automatic aspects of
exception handling. Complex exception handlers (for example, nested
exception handlers) must follow additional precautions.
handlers. The hardware itself accomplishes much of the status- and
register-preservation overhead required by an exception handler. Simple
exception handlers can substantially ignore all automatic aspects of
exception handling. Complex exception handlers (for example, nested
exception handlers) must follow additional precautions.
Simple Exception Handlers
An exception handler is considered simple if it obeys the following rules:
■
It does not re-enable interrupts.
■
It does not use SAVE or RESTORE (either directly or by calling
subroutines that use SAVE or RESTORE).
subroutines that use SAVE or RESTORE).
■
It does not use any TRAP instructions (or call any subroutines that
use TRAP instructions).
use TRAP instructions).
■
It does not alter the contents of registers %g0..%g7, or %i0..%i7.
Any exception handler that obeys these rules need not take special
precautions with ISTATUS or the return address in %o7. A simple
exception handler need not be concerned with CWP or register-window
management.
precautions with ISTATUS or the return address in %o7. A simple
exception handler need not be concerned with CWP or register-window
management.