Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
Altera Corporation
37
32323232
32-Bit Instruction Set
2
3
2
-B
it In
st
st
ru
ctio
n
n
Se
t
t
AND
Bitwise Logical AND
Operation:
Not preceded by PFX:
RA
RA
← RA & RB
Preceded by PFX:
RA
RA
←
RA & (0x00.00 : K : IMM5)
Assembler Syntax:
Not preceded by PFX:
AND %rA,%rB
Preceded by PFX:
PFX %hi(const)
AND %rA,%lo(const)
Example:
Not preceded by PFX:
AND %g0,%g1 ; %g0 gets %g1 & %g0
Preceded by PFX:
PFX %hi(16383)
AND %g0,%lo(16383) ; AND %g0 with 16383
Description:
Not preceded by PFX:
Logically-AND the individual bits in RA with the corresponding bits in RB; store
the result in RA.
Preceded by PFX:
When prefixed, the RB operand is replaced by an immediate constant formed by
concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This
16-bit value (zero-extended to 32 bits) is bitwise-ANDed with RA, and the result
is written back into RA.
Logically-AND the individual bits in RA with the corresponding bits in RB; store
the result in RA.
Preceded by PFX:
When prefixed, the RB operand is replaced by an immediate constant formed by
concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This
16-bit value (zero-extended to 32 bits) is bitwise-ANDed with RA, and the result
is written back into RA.
Condition Codes:
Flags:
N: Result bit 31
Z: Set if result is zero, cleared otherwise
Z: Set if result is zero, cleared otherwise
Instruction Format:
RR, Ri5
Instruction Fields:
A = Register index of RA operand
B = Register index of RB operand
B = Register index of RB operand
IMM5 = 5-bit immediate value
Not preceded by PFX (RR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
1
0
B
A
Preceded by PFX (Ri5)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
1
0
IMM5
A
N
V
Z
C
∆
–
∆
–