Excalibur electronic A-MNL-NIOSPROG-01.1 用户手册
Altera Corporation
59
32323232
32-Bit Instruction Set
2
3
2
-B
it In
st
st
ru
ctio
n
n
Se
t
t
LD
Load 32-bit Data From Memory
Operation:
Not preceded by PFX:
RA
← Mem32[align32(RB)]
Preceded by PFX:
RA
← Mem32[align32(RB + σ(K) × 4))]
Assembler Syntax:
LD %rA,[%rB]
Example:
Not preceded by PFX:
LD %g0,[%i3] ; load word at [%i3] into %g0
Preceded by PFX:
PFX 7 ; word offset
LD %g0,[%i3] ; load word at [%i3+28] into %g0
Description:
Not preceded by PFX:
Loads a 32-bit data value from memory into RA. Data is always read from a word-
Loads a 32-bit data value from memory into RA. Data is always read from a word-
aligned address given by bits 31..2 of RB (the two LSBs of RB are ignored).
Preceded by PFX:
Preceded by PFX:
The value in K is sign-extended and used as a word-scaled, signed offset. This
offset is added to the base-address RB (bits 1..0 ignored), and data is read from
offset is added to the base-address RB (bits 1..0 ignored), and data is read from
the resulting word-aligned address.
Condition Codes:
Flags: Unaffected
Instruction Format:
RR
Instruction Fields:
A = Register index of operand RA
B = Register index of operand RB
B = Register index of operand RB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
1
1
0
B
A
N
V
Z
C
−
−
−
−