Philips S1D13505 用户手册

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页码 556
Page 94
Epson Research and Development
Vancouver Design Center
S1D13505
Hardware Functional Specification
X23A-A-001-14
Issue Date: 01/02/02
7.5.10  16-Bit TFT/D-TFD Panel Timing
Figure 7-42: 16-Bit TFT/D-TFD Panel Timing
VDP 
= Vertical Display Period 
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
VNDP
= Vertical Non-Display Period 
= (REG[0Ah] bits [5:0]) + 1
HDP
= Horizontal Display Period 
= ((REG[04h] bits [6:0]) + 1)*8Ts
HNDP 
= Horizontal Non-Display Period 
= HNDP
1
 + HNDP
2
= ((REG[05h] bits [4:0]) + 1)*8Ts
FPFRAME
FPLINE
LINE1
LINE480
1-1
1-1
1-1
1-2
1-2
1-2
1-640
1-640
1-640
FPLINE
FPSHIFT
DRDY
R[5:1], G[5:0], B[5:1]
R[5:1]
G [5:0]
B[5:1]
VDP
DRDY
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
VNDP
HDP
HNDP
1
HNDP
2
LINE480