Philips S1D13505 用户手册
Epson Research and Development
Page 17
Vancouver Design Center
Hardware Functional Specification
S1D13505
Issue Date: 01/02/02
X23A-A-001-14
.
Figure 3-5: Typical System Diagram (Generic Bus)
.
Figure 3-6: Typical System Diagram (NEC VR41xx (MIPS) Bus)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLK
I
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
Generic
BUS
BUS
RESET#
D[15:0]
RD#
WAIT#
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[27:21]
CSn#
WE1#
LCDPWR
WE
#
A
[11:
0]
D[
15:
0]
R
AS#
1Mx16
LCA
S
#
U
C
AS#
M
A
[11:
0]
M
D
[15:
0]
WE
#
R
AS#
LCA
S
#
U
C
AS#
FPM/EDO-DRAM
Decoder
WE0#
WE0#
Power
Management
SU
SPE
N
D
#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
Display
IREF
IREF
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLK
I
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
MIPS
BUS
BUS
RESET
D[15:0]
MEMR#
RDY
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[25:21]
CSn#
SBHE#
LCDPWR
WE
#
A
[11:
0
]
D[
15:
0]
R
AS#
1Mx16
L
C
AS#
UCA
S
#
M
A
[11:
0
]
M
D
[15:
0]
WE
#
R
AS#
L
C
AS#
UCA
S
#
FPM/EDO-DRAM
Decoder
WE0#
MEMW#
Power
Management
SU
SP
EN
D
#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
Display
IREF
IREF
VDD