Philips S1D13505 用户手册

Page 7

Vancouver Design Center

13505CFG Configuration Program

S1D13505

Issue Date: 01/03/29 

X23A-B-001-04

13505CFG provides a series of tabs which can be selected at the top of the main window. 
Each tab allows the configuration of a specific aspect of S1D13505 operation.

The tabs are labeled “General”, “Preference”, “Memory”, “Clocks”, “Panel”, “CRT”, and 
“Registers”. The following sections describe the purpose and use of each of the tabs.

The General tab contains S1D13505 evaluation board specific information. The values 
presented are used for configuring HAL based executable utilities. The settings on this tab 
specify where in CPU address space the registers and display buffer are located.

Decode Addresses

Selecting one of the listed evaluation platforms changes 
the values for the “Register address” and “Display 
buffer address” fields. The values used for each evalu-
ation platform are examples of possible implementa-
tions as used by the Epson S1D13505 evaluation 
boards. If your hardware implementation differs from 
the addresses used, select the User-Defined option and 
enter the correct addresses for “Register address” and 
“Display buffer address”.

Decode Addresses

Register Address

Display Buffer Address