Philips S1D13505 用户手册

Page 15

Vancouver Design Center

S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual

S1D13505

Issue Date: 01/02/05 

X23A-G-004-05

The S1D13505 supports 256K x 16 as well as 1M x 16 FPM/EDO-DRAM in symmetrical and 
asymmetrical formats.

The S5U13505B00C board supports a 5.0V 1M x 16 symmetrical EDO-DRAM (42-pin SOJ 
package). This provides a 2M byte display buffer.

This board utilizes the MIPS/ISA Interface of the S1D13505 (see the S1D13505 Hardware 
Functional Specification, document number X23A-A-001-xx).

All required decode logic is provided through a 22V10 PAL (U4, socketed). 

The S1D13505 supports up to a 40.0Mhz input clock frequency. A 40.0MHz oscillator (U2, 
socketed) is provided on the S5U13505 board as the clock (CLKI) source. 

The S1D13505 supports 4 and 8-bit, dual and single, monochrome passive LCD panels. All 
necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals on the 
cable are alternated with grounds to reduce crosstalk and noise.

Refer to Table 3-1 “LCD Signal Connector (J6)” on page 9 for connection information.

The S1D13505 directly supports 4, 8 and 16-bit, dual and single, color passive LCD panels. All the 
necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals on the 
cable are alternated with grounds to reduce crosstalk and noise.

Refer to Table 3-1 “LCD Signal Connector (J6)” on page 9 for connection information.