Philips S1D13505 用户手册
Page 44
Epson Research and Development
Vancouver Design Center
S1D13505
Hardware Functional Specification
X23A-A-001-14
Issue Date: 01/02/02
7.1.2 SH-3 Interface Timing
Figure 7-2: SH-3 Timing
Note
The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is
selected.
selected.
Note
The SH-3 Wait State Control Register for the area in which the S1D13505 resides must be set to
a non-zero value.
a non-zero value.
t1
t2
t3
t4
t10
t11
t15
t5
t6
t7
t8
t9
t12
t16
t13
t14
CKIO
A[20:0], M/R#
CSn#
RD/WR#
RD#
D[15:0](read)
BS#
WAIT#
WEn#
D[15:0](write)
t12