Philips S1D13505 用户手册

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Vancouver Design Center

S1D13505

Interfacing to the Toshiba MIPS TX3912 Processor

X23A-G-010-04

Issue Date: 01/02/05

The host interface control signals of the S1D13505 are asynchronous with respect to the 
S1D13505 bus clock. This gives the system designer full flexibility to choose the
appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks 
should be the same, whether to use DCLKOUT as clock source, and whether an external or 
internal clock divider is needed, should be based on the desired:

• pixel and frame rates.

• power budget.

• part count.

• maximum S1D13506 clock frequencies.

The S1D13505 also has internal CLKI dividers providing additional flexibility.

The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other 
configuration data on the rising edge of RESET#. For details on configuration, refer to the 
S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

The table below shows those configuration settings relevant to the Toshiba TX3912 host 
bus interface.

MD0

8-bit host bus interface

16-bit host bus interface

MD[3:1]

111 = Toshiba TX3912 host bus interface if Alternate host bus interface is selected

MD4

Little Endian

Big Endian

MD5

WAIT# is active high (1 = insert wait state)

WAIT# is active low (0 = insert wait state)

MD11

Alternate host bus interface selected

Primary host bus interface selected

MD12

BUSCLK input divided by two: use with DCLKOUT

BUSCLK input not divided: use with external oscillator

= configuration for Toshiba TX3912 host bus interface