Philips S1D13505 用户手册
Page 8
Epson Research and Development
Vancouver Design Center
S1D13505
Interfacing to the NEC VR4121™ Microprocessor
X23A-G-011-04
Issue Date: 01/02/05
2 Interfacing to the NEC V
R
4121
2.1 The NEC V
R
4121 System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows CE based embedded consumer applications in mind, the VR4121 offers a highly
integrated solution for portable systems. This section provides an overview of the operation
of the CPU bus in order to establish interface requirements.
typical of modern microprocessors. Designed with external LCD controller support and
Windows CE based embedded consumer applications in mind, the VR4121 offers a highly
integrated solution for portable systems. This section provides an overview of the operation
of the CPU bus in order to establish interface requirements.
2.1.1 Overview
The NEC VR4121 is designed around the RISC architecture developed by MIPS. This
microprocessor is based on the 166MHz VR4120 CPU core which supports 64-bit
processing. The CPU communicates with the Bus Control Unit (BCU) using its internal
SysAD bus. The BCU in turn communicates with external devices using its ADD and
DATA buses which can be dynamically sized to 16 or 32-bit operation.
microprocessor is based on the 166MHz VR4120 CPU core which supports 64-bit
processing. The CPU communicates with the Bus Control Unit (BCU) using its internal
SysAD bus. The BCU in turn communicates with external devices using its ADD and
DATA buses which can be dynamically sized to 16 or 32-bit operation.
The NEC VR4121 has direct support for an external LCD controller. Specific control
signals are assigned for an external LCD controller providing an easy interface to the CPU.
A 16M byte block of memory is assigned for the LCD controller and its own chip select
and ready signals are available. Word or byte accesses are controlled by the system high
byte signal (SHB#).
signals are assigned for an external LCD controller providing an easy interface to the CPU.
A 16M byte block of memory is assigned for the LCD controller and its own chip select
and ready signals are available. Word or byte accesses are controlled by the system high
byte signal (SHB#).