Philips S1D13505 用户手册
Page 48
Epson Research and Development
Vancouver Design Center
S1D13505
Hardware Functional Specification
X23A-A-001-14
Issue Date: 01/02/02
7.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030)
Figure 7-4: MC68030 Timing
Note
The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is
selected.
selected.
A[20:0]
AS#
DS#
D[31:16](write)
SIZ[1:0] M/R#
R/W#
DSACK1#
CLK
t1
t2
t3
t4
t10
t7
CS#
t6
t8
t5
D[31:16](read)
t11
t12
t13
t9
t14
t15
t16
t17