Philips S1D13505 用户手册
Epson Research and Development
Page 9
Vancouver Design Center
Interfacing to the NEC V832™ Microprocessor
S1D13505
Issue Date: 01/02/05
X23A-G-012-02
2.1.2 Access Cycles
Once an address in the appropriate range is placed on the external address bus (A[23:1]),
the corresponding chip select (CSn) is driven low. The read or write enable signals (IORD
or IOWR) are driven low and READY is driven low by the S1D13505 to insert wait states
into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.
the corresponding chip select (CSn) is driven low. The read or write enable signals (IORD
or IOWR) are driven low and READY is driven low by the S1D13505 to insert wait states
into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.
The following figure illustrates typical NEC V832 memory-mapped IO access cycles.
Figure 2-1: NEC V832 Read/Write Cycles
SDCLKOUT
A[23:1]
CSn
IORD,
READY
VALID
VALID
Hi-Z
Hi-Z
D[15:0]
D[15:0]
(write)
(read)
LLBEN,
LUBEN
IOWR
VALID